eMemory Technology Assigned Five Patents

Memory cell and array structure of NVM and associated control method
eMemory Technology Inc. Hsin-Chu, Taiwan, has been assigned a patent (12283326) developed by Ku; Wei-Ming, Hsinchu County, Taiwan, for “memory cell and array structure of non-volatile memory and associated control method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory cell of a non-volatile memory includes a select transistor, a floating gate transistor, a first capacitor, a switching transistor and a second capacitor. A first drain/source terminal of the select transistor is connected with a source line. A gate terminal of the select transistor is connected with a word line. The two drain/source terminals of the floating gate transistor are respectively connected with a second drain/source terminal of the select transistor and a bit line. The first capacitor is connected between a floating gate of the floating gate transistor and an erase node. The two drain/source terminals of the switching transistor are respectively connected with the erase node and an erase line. The gate terminal of the switching transistor is connected with a control line. The second capacitor is connected between the erase node and a boost line.”

The patent application was filed on 2023-02-24 (18/113675).

Programming method of NVM cell
eMemory Technology Inc. Hsin-Chu, Taiwan, has been assigned a patent (12255645) developed by Hsu; Chia-Jung, Lo; Chun-Yuan, Li; Chun-Hsiao, and Lung; Chang-Chun, Hsinchu County, Taiwan, for “programming method of non-volatile memory cell.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A programming method of a non-volatile memory cell is provided. The non-volatile memory cell includes a memory transistor. Firstly, a current limiter is provided, and the current limiter is connected between a drain terminal of the memory transistor and a ground terminal. Then, a program voltage is provided to a source terminal of the memory transistor, and a control signal is provided to a gate terminal of the memory transistor. In a first time period of a program action, the control signal is gradually decreased from a first voltage value, so that the memory transistor is firstly turned off and then slightly turned on. When the memory transistor is turned on, plural hot electrons are injected into a charge trapping layer of the memory transistor.”

The patent application was filed on 2023-07-28 (18/227409).

Memory cell of charge-trapping NVM
eMemory Technology Inc. Hsin-Chu, Taiwan, has been assigned a patent (12199160) developed by Hsu; Chia-Jung, and Sun; Wein-Town, Hsinchu County, Taiwan, for “memory cell of charge-trapping non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory cell of a charge-trapping non-volatile memory includes a semiconductor substrate, a well region, a first doped region, a second doped region, a gate structure, a protecting layer, a charge trapping layer, a dielectric layer, a first conducting line and a second conducting line. The first doped region and the second doped region are formed under a surface of the well region. The gate structure is formed over the surface of the well region. The protecting layer formed on the surface of the well region. The charge trapping layer covers the surface of the well region, the gate structure and the protecting layer. The dielectric layer covers the charge trapping layer. The first conducting line is connected with the first doped region. The second conducting line is connected with the second doped region.”

The patent application was filed on 2022-12-12 (18/079081).

NVM and voltage detecting circuit thereof
eMemory Technology Inc. Hsin-Chu, Taiwan, has been assigned a patent (12094559) developed by Lin; Zhe-Yi, Hsinchu County, Taiwan, for “memory cell of charge-trapping non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A voltage detecting circuit for a non-volatile memory is provided. When a standby signal is not asserted, a power supply unit of the non-volatile memory provides an array voltage to a first node. The voltage detecting circuit includes an initial voltage generator, a capacitor, a latch and a combinational logic circuit. The initial voltage generator receives an inverted standby signal and an enable signal. An output terminal of the initial voltage generator is connected with a second node. The capacitor is coupled between the first node and the second node. An input terminal of the latch is connected with the second node. An output terminal of the latch is connected with a third node. An input terminal of the combinational logic circuit is connected with the third node. An output terminal of the combinational logic circuit generates the enable signal.”

The patent application was filed on 2022-11-30 (18/072014).

Resistive memory cell and associated cell array structure
eMemory Technology Inc. Hsin-Chu, Taiwan, has been assigned a patent (12069873) developed by Lai; Tsung-Mu, and Chang; Wei-Chen, Hsinchu County, Taiwan, for “resistive memory cell and associated cell array structure.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A cell array structure includes a first resistive memory cell. The first resistive memory cell includes a well region, a first doped region, a merged region, a first gate structure, a second gate structure and a first metal layer. The first doped region is formed under a surface of the well region. The merged region is formed under the surface of the well region. The first gate structure is formed over the surface of the well region between the first doped region and the merged region. The first gate structure includes a first insulation layer and a first conductive layer. The second gate structure is formed over the merged region. The second gate structure includes a second insulation layer and a second conductive layer. The first metal layer is connected with the first doped region.”

The patent application was filed on 2021-08-31 (17/462040).