SK hynix NAND Product Solutions Assigned Four Patents

SSD managed host write atomicity with arbitrary transfer length
SK hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12260126) developed by Li; Peng, Beaverton, OR, Khan; Jawad, Portland, OR, Ellis; Jackson, Fort Collins, CO, and Trika; Sanjeev, Portland, OR, for a “SSD managed host write atomicity with arbitrary transfer length.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a primary persistent storage with a first type of media and a nonvolatile memory buffer with a second type of media that is different from the first type of media, store metadata for incoming write data in the nonvolatile memory buffer, store other data for the incoming write data in the primary persistent storage, and provide both runtime and power-fail write atomicity for the incoming write data. Other embodiments are disclosed and claimed.”

The patent application was filed on 2024-03-27 (18/618532).

Eliminating garbage collection in SSDs
SK hynix NAND Product Solutions Corp., San Jose, CA, has been assigned a patent (12260093) developed by Kalwitz; George, Mead, CO, for “systems and methods for eliminating garbage collection in solid-state drives (SSDs).“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems and methods for eliminating garbage collection in solid-state drives (SSDs) of a data center are disclosed herein. A data placement block (DPB) size is determined. An SSD receives, from a host device, a write command specifying a virtual logical block address (LBA). The SSD identifies a DPB based on the virtual LBA of the write command. The SSD causes data associated with the write command to be written to an erasable unit of memory of the SSD based on the identified DPB, and causes an association between the erasable unit of memory of the SSD and the virtual LBA of the write command to be stored.”

The patent application was filed on 2022-12-28 (18/089994).

Data structure reconfiguration for LDPCs in memory systems
SK hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12231147) developed by Kwok; Zion, Burnaby, CA, for a “data structure reconfiguration for low density parity checks (LDPCs) in memory systems.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This application is directed to compressing check node data for an electronic device. The electronic device identifies a check node corresponding to a subset of codeword symbols in a block of data and determines check node data that indicates a likelihood of the subset of codeword symbols being erroneous. A set of data bits are determined based on a value combination of data items of the check node data to uniquely identify the value combination among a set of selected value combinations according to a predefined relationship. The electronic device stores, in a memory block, the set of data bits representing the data items of the check node data of the check node. Each data item requires more data bits to represent all possible values of the respective data item than data bits of the set of data bits.”

The patent application was filed on 2023-08-22 (18/236861).

Systems, methods, and media for controlling background wear leveling in SSDs
SK hynix NAND Product Solutions Corp., San Jose, CA, has been assigned a patent (12223172) developed by Dreyer; David G., Oronoco, MN, Pelster; David J., Longmont, CO, Golez; Mark Anthony Sumabat, Folsom, CA, and Govindarajan; Bhargavi, Milpitas, CA, for “systems, methods, and media for controlling background wear leveling in solid-state drives.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Mechanisms for controlling background wear leveling are provided, including: increasing a first counter; comparing the first counter to a first threshold; and in response to the first counter meeting the first threshold: decreasing the first counter by a value of the first threshold; and triggering background wear leveling. In some embodiments, the first counter is increased in response to receiving a write trigger. In some embodiments, the first threshold is based upon a page size and a number of planes of physical media of an SSD. In some embodiments, the mechanisms further comprise: incrementing a second counter in response to receiving a host write trigger; comparing the second counter to a second threshold; and in response to the second counter meeting the second threshold, decreasing the second counter by the second threshold, wherein the increasing the first counter is performed in response to the second counter meeting the second threshold.”

The patent application was filed on 2022-12-28 (18/090347).