R&D: Investigation of Cell Variation Effect on Z-Interference in Charge-Trap-Based 3-D NAND Flash Memory

IEEE Transactions on Electron Devices has published an article written by Sangmin Ahn, Hyungjun Jo, Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea, Sechun Park, Jongwoo Kim, NAND Design Team, SK Hynix Inc., Icheon-si, South Korea, and Hyungcheol Shin, Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea, and Integra Semiconductor Ltd., Seoul, South Korea.

Abstract: “In this article, we investigated the effects of cell variations, specifically the variations in gate length (L_g), spacer length (L_s), filler oxide thickness (T_f), channel thickness (T_ch), tunneling oxide thickness (T_tox), charge trap nitride thickness (T_ctn), and blocking oxide thickness (T_box), on the z-direction interference (Z-interference) in charge-trap-based 3-D NAND flash memory. Most previous studies have primarily focused on Z-interference degradation caused by the physical scaling of Z-dimensions, which has become a major obstacle in developing advanced multilevel cell technologies such as quad-level cell (QLC) and penta-level cell (PLC). However, with the physical scaling issue, the limitations of the fabrication process are causing cell variation. Nevertheless, research on Z-interference resulting from cell variation remains insufficient in existing studies. Therefore, we analyzed the impact of cell variation on threshold voltage (V_th) distribution through the Monte Carlo simulation, incorporating technology computer-aided design (TCAD) and experimental data. These results not only offer a comprehensive understanding of Z-interference but also provide valuable insights for formulating process design guidelines.“