Silicon Motion Assigned Twelve Patents

Method and non-transitory computer-readable storage medium and apparatus for decoding low-density parity-check (LDPC) code
Silicon Motion, Inc., Zhubei, Taiwan, has been assigned a patent (12231146) developed by Teng; Duen-Yih, Taoyuan, Taiwan, for “method and non-transitory computer-readable storage medium and apparatus for decoding low-density parity-check (LDPC) code.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for decoding a Low-Density Parity-Check (LDPC) code. The method, which is performed by a processing unit in an LDPC decoder, includes the following steps: determining whether a bit flipping algorithm when decoding a codeword enters a trapping state after an observation period during which a sequential selection strategy is used; and modifying a scheduling strategy to a non-sequential selection strategy and performing the bit flipping algorithm on the codeword under the non-sequential selection strategy when the bit flipping algorithm enters the trapping state. The codeword is divided into chunks in fixed-length and the sequential selection strategy indicates sequentially selecting the chunks in the codeword, so that the bit flipping algorithm is performed on one selected chunk only each time. The non-sequential selection strategy indicates an arbitrary selection combination of the chunks in the codeword, which is different from that under the sequential selection strategy.”

The patent application was filed on 2023-07-11 (18/220464).

Performing data fragmentation reduction control of memory device in predetermined communications architecture with aid of fragmentation information detection, and associated computer-readable medium
Silicon Motion, Inc., Zhubei, Taiwan, has been assigned a patent (12229413) developed by Shih; Po-Yi, Hsinchu County, Taiwan, for “method and apparatus for performing data fragmentation reduction control of memory device in predetermined communications architecture with aid of fragmentation information detection, and associated computer-readable medium.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for performing data fragmentation reduction control of a memory device in a predetermined communications architecture with aid of fragmentation information detection, associated apparatus and computer-readable medium are provided. The method may include: utilizing a memory controller to receive a first command from a host device through a transmission interface circuit of the memory controller; utilizing the memory controller to perform discontinuity-related calculation to generate a discontinuity-related calculation result for generating a data fragmentation degree, and send a first response; utilizing the memory controller to receive a second command from the host device through the transmission interface circuit; and utilizing the memory controller to send a second response to the host device through the transmission interface circuit to return the data fragmentation degree to the host device, for selectively performing data fragmentation reduction according to a determination result of the host device.”

The patent application was filed on 2022-10-27 (17/974546).

Programming data arranged to undergo specific stages into flash memory based on virtual carriers
Silicon Motion, Inc., Zhubei, Taiwan, has been assigned a patent (12223199) developed by Chiu; Shen-Ting, Miaoli County, Taiwan, for “method and apparatus for programming data arranged to undergo specific stages into flash memory based on virtual carriers.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The invention relates to a method, and an apparatus for programming data into flash memory. The method includes: reading operating settings of a virtual carrier; setting a redundant array of independent disks (RAID) engine for driving the RAID engine to complete a designated encryption or encoding operation on first data associated with the virtual carrier when the operation settings indicate that the first data associated with the virtual carrier need to go through a mid-end processing stage; and sending a programming index to a data access engine for driving the data access engine to read a programming table from the SRAM, and program the second data associated with the virtual carrier into a designated address in a flash module when the operation settings indicate that the second data associated with the virtual carrier need to go through the back-end processing stage.”

The patent application was filed on 2022-08-02 (17/879232).

Detecting errors during data encryption
Silicon Motion, Inc., Zhubei, Taiwan, has been assigned a patent (12225126) developed by Wu; Wun-Jhe, Kinmen County, Taiwan, Chen; Po-Hung, Taoyuan, Taiwan, Cheng; Chiao-Wen, Yu; Jiun-Hung, and Liu; Chih-Wei, Zhubei, Taiwan, for “apparatus and method for detecting errors during data encryption.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The invention introduces an apparatus for detecting errors during data encryption. The apparatus includes a key generation circuitry and a key-error detection circuitry. The key generation circuitry is arranged operably to realize a key expansion operation for generating multiple round keys based on a root key in an encryption algorithm, where the encryption algorithm encodes plaintext or an intermediate encryption result with one round key in a corresponding round. The error detection circuitry is arranged operably to: calculate redundant data corresponding to each round key; and output an error signal to a processing unit when finding that any round key does not match corresponding redundant data at a check point during the key expansion operation.”

The patent application was filed on 2022-12-07 (18/076615).

Memory controller and data processing method for processing disordered read-out data
Silicon Motion, Inc., Zhubei, Taiwan, has been assigned a patent (12223173) developed by Ye; Bo-Chang, Kaohsiung, Taiwan, Chen; I-Ta, New Taipei, Taiwan, Chen; Wen-Shu, Taipei, Taiwan, and Kuo; Kuo-Cyuan, Hsinchu County, Taiwan, for “memory controller and data processing method for processing disordered read-out data.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A data processing method includes reading a memory device in response to a read command to respectively read multiple portions of predetermined data; respectively writing the portions in a buffer memory to complete data transfers of the portions of the predetermined data; sequentially providing access information corresponding to each portion of the predetermined data in response to completion of the data transfer of the corresponding portion; obtaining the access information of the predetermined data and accordingly generating multiple descriptors in chronological order of obtaining the access information; receiving and buffering the descriptors in a descriptor pool; sequentially selecting a latest descriptor from the descriptor pool according to a tag value and providing the latest descriptor to a direct memory access engine; and reading the buffer memory according to the latest descriptor to obtain at least a portion of the predetermined data by the direct memory access engine.”

The patent application was filed on 2023-03-02 (18/116801).

Memory controller and method for controlling output of debug messages
Silicon Motion, Inc., Zhubei, Taiwan, has been assigned a patent (12222856) developed by Fang; Hong-Ren, and Wang; Hao-Hsuan, Hsinchu County, Taiwan, for “memory controller and method for controlling output of debug messages.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory controller coupled to a memory device for accessing the memory device and includes a Universal Asynchronous Receiver/Transmitter (UART) and a microprocessor. The microprocessor is coupled to the UART and configured to control access operations of the memory device. The microprocessor is configured to perform an interrupt service routine in response to an interrupt. When performing the interrupt service routine, the microprocessor is configured to determine whether a predetermined signal has been received by a specific pin and when determining that the predetermined signal has been received by the specific pin, the microprocessor is configured to output a debug message through a transmitting terminal of the UART.”

The patent application was filed on 2023-06-26 (18/213899).

Performing mapping table management of memory device in predetermined communications architecture with aid of table analysis
Silicon Motion, Inc., Zhubei, Taiwan, has been assigned a patent (12222870) developed by Lee; Jie-Hao, Hsinchu County, Taiwan, and Chen; Chun-Ju, Taichung, Taiwan, for “method and apparatus for performing mapping table management of memory device in predetermined communications architecture with aid of table analysis.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for performing mapping table management of a memory device in a predetermined communications architecture with aid of table analysis and associated apparatus are provided. The method may include: utilizing the memory controller to receive a first command from a host device through a transmission interface circuit of the memory controller; and in response to the first command, loading a local logical-to-physical (L2P) address mapping table from a non-volatile (NV) memory into a volatile memory within the memory controller to be a temporary L2P address mapping table, changing multiple L2P table entries in the temporary L2P address mapping table to be multiple updated L2P table entries in a group-by-group manner, rather than an entry-by-entry manner, and updating the local L2P address mapping table in the NV memory according to the multiple updated L2P table entries of the temporary L2P address mapping table.”

The patent application was filed on 2023-03-02 (18/116311).

Driving RAID engine
Silicon Motion, Inc., Zhubei, Taiwan, has been assigned a patent (12210775) developed by Lee; Lien-Yu, Zhubei, Taiwan, and Chiu; Shen-Ting, Miaoli County, Taiwan, for “apparatus and method for driving redundant array of independent disks (RAID) engine.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The invention is related to an apparatus and a method for driving redundant array of independent disks (RAID) engine. The method, performed by a RAID controller in a RAID pre-processor, including: completing a driving operation for performing a series of physical-layer signal interactions with a RAID engine according to a driving value in the configuration register. The driving value corresponds to a command issued by a processing unit. The processing unit performs an operation irrelevant from an encoding or a decoding of a parity of a page group in parallel of the driving operation by the RAID controller in coordination with the RAID engine.”

The patent application was filed on 2022-11-10 (17/984691).

Method and non-transitory computer-readable storage medium and apparatus for dynamically updating optimization read voltage table
Silicon Motion, Inc., Zhubei, Taiwan, has been assigned a patent (12204763) developed by Chen; Chun-Yi, Hsinchu County, Taiwan, and Chang; Hsiao-Te, Zhubei, Taiwan, for “method and non-transitory computer-readable storage medium and apparatus for dynamically updating optimization read voltage table.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for dynamically updating an optimization read voltage (RV) table. The method includes: obtaining a data-read transaction and replying with the data-read transaction to a host side after listening to a first request for read-performance data, which is issued by the host side, thereby enabling the data-performance transaction to be used in an update of the optimization RV table for a designated memory-cell type; and programming multiple records of an updated optimization RV table for the designated memory-cell type into a designated location of the NAND-flash module after listening to a second request for updating the optimization RV table for the designated memory-cell type, which is issued by the host side. The data-read transaction includes a current environmental parameter of a NAND-flash module, the designated memory-cell type and a bit error rate (BER). Each record includes one set of RV parameters and an environmental parameter associated with the set of RV parameters.”

The patent application was filed on 2022-12-14 (18/080852).

Method and non-transitory computer-readable storage medium and apparatus for scheduling and executing host data-update commands
Silicon Motion, Inc., Zhubei, Taiwan, has been assigned a patent (12197786) developed by Yao; Yu-Hsien, Zhubei, Taiwan, for “method and non-transitory computer-readable storage medium and apparatus for scheduling and executing host data-update commands.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The invention introduces a method for scheduling and executing host data-update commands. A first queue and a second queue are provided. The first queue includes first host data-update commands each including a first logical address. The second queue includes second host data-update commands each including a second logical address. A third host data-update command including a third logical address is generated and is labeled as a first type of host data-update command according to a host command received from a host side. All the first host data-update commands of the first queue are popped out and executed in response that the third logical address is the same as any first logical address. All the second host data-update commands of the second queue are popped out and executed in response that the third logical address is the same as any second logical address.”

The patent application was filed on 2023-08-04 (18/230364).

Data storage system and parameter margin evaluation method
Silicon Motion, Inc., Zhubei, Taiwan, has been assigned a patent (12189964) developed by Shih; Po-Yi, Hsinchu County, Taiwan, for “data storage system and parameter margin evaluation method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for evaluating a margin of at least one parameter utilized by a transmission interface includes: step (A) setting a value of a first parameter utilized by a host device to a first test value selected from a first group; (B) setting a value of a second parameter utilized by a data storage device to a second test value selected from a second group; (C) controlling the data storage device to perform a predetermined testing procedure to test whether the data storage device functions normally when the first test value and the second test value are applied; and (D) changing the first test value or the second test value and re-performing steps (A) to (C), wherein step (D) is repeatedly performed until all the test values in the first group and the second group have been tested.”

The patent application was filed on 2022-12-05 (18/074527).

Storage device controller and method capable of allowing incoming out-of-sequence write command signals
Silicon Motion, Inc., Zhubei, Taiwan, has been assigned a patent (12189991) developed by Chen; Li-Chi, Taichung, Taiwan, and Jou; Yen-Yu, Taoyuan, Taiwan, for “storage device controller and method capable of allowing incoming out-of-sequence write command signals.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of a storage device controller includes: using an interface circuit for receiving and storing different write address information of different write command signals sent from a host device, the different write address information being out of sequence; and, using multiple processor cores to rearrange the different write address information in sequence and then write data into at least one storage zone according to the different write address information rearranged in sequence.”

The patent application was filed on 2022-10-02 (17/958430).