SK hynix NAND Product Solutions Assigned Eleven Patents

NAND-based storage device with partitioned nonvolatile write buffer
SK hynix NAND Product Solutions Corp., San Jose, CA, has been assigned a patent (12197776) developed by Wysoczanski; Michal, Koszalin, Poland, Karkra; Kapil, Chandler, AZ, Wysocki; Piotr, Gdansk, Poland, Ramalingam; Anand S., Portland, OR, for a “NAND-based storage device with partitioned nonvolatile write buffer.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.”

The patent application was filed on 2023-05-18 (18/199135).

Reducing impact of drive parameter writes on SSD performance
SK hynix NAND Product Solutions Corp., San Jose, CA, has been assigned a patent (12189504) developed by Gangadhar; Sarvesh Varakabe, San Jose, CA, Pelster; David J., Longmont, CO, Govindarajan; Bhargavi, Milpitas, CA, Rajagopal; Archana, El Dorado Hills, CA, Golez; Mark Anthony Sumabat, and Wakchaure; Yogesh, Folsom, CA, for “systems, methods, and media for reducing the impact of drive parameter writes on solid state drive performance.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Mechanisms for reducing the impact of drive parameter writes on solid state drive (SSD) performance are provided, the methods including: saving one or more SSD drive parameters of an SSD to volatile memory of the SSD using an SSD controller; detecting a power-loss condition in the SSD; and copying the one or more SSD drive parameters from the volatile memory of the SSD to non-volatile memory of the SSD. In some embodiments, the SSD is a NAND SSD. In some embodiments, the one or more SSD drive parameters include one or more of: a drive health parameter, a drive internal statistic, drive thermal information, drive debug information, a number of host and non-volatile memory read and writes, media error handling data, temperature and throttle information, and firmware download information. In some embodiments, the volatile memory is one or more of: random-access memory and dynamic random-access memory.”

The patent application was filed on 2022-09-06 (17/903854).

Media for recovering worker shares from read prioritization
SK hynix NAND Product Solutions Corp., San Jose, CA, has been assigned a patent (12182410) developed by de Vries; Jonathan, Folsom, CA, and Vemula; Neelesh, Santa Clara, CA, for “systems, methods, and media for recovering worker shares from read prioritization.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Recovering worker shares from read prioritization including: while read accesses (RA) to a storage device (SD) are being prioritized over write accesses (WA) to the SD: determining a first count of RA to the SD; performing a first adjusting of a base read share percentage (RSP) to a first adjusted RSP for RA to the SD based on the first count of RA; and controlling read access to the SD based on the first adjusting; determining that RA to the SD have completed being prioritized over WA to the SD; and after RA to the SD have completed being prioritized: determining a second count of WA to the SD; performing a second adjusting of the first adjusted RSP to a second adjusted RSP for RA to the SD based on the second count of WA; and controlling write access to the SD based on the second adjusting.”

The patent application was filed on 2022-09-21 (17/949378).

Techniques to predict or determine time-to-ready for storage device
SK hynix NAND Product Solutions Corp., San Jose, CA, has been assigned a patent (12175101) developed by Tarango; Joseph D., and Baca; Jim S., Longmont, CO, for a “techniques to predict or determine time-to-ready for a storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Examples may include techniques to predict or determine time-to-ready (TTR) for a storage device. TTR may be predicted or determined based on operating information included in a snapshot associated with a first time interval during operation of the storage device. The TTR predicted or determined indicates an amount of time the storage device will be at an operational state following a power loss recover of the storage device.”

The patent application was filed on 2023-06-08 (18/207548).

Improve read latency of multi-threshold level cell block-based NVM
SK hynix NAND Product Solutions Corp., San Jose, CA, has been assigned a patent (12154620) developed by Chen; Lei, Sunnyvale, CA, Wakchaure; Yogesh B., Madraswala; Aliasgar S., Folsom, CA, Guo; Xin, San Jose, CA, and Uhlman; Cole, Vancouver, Canada, for “method and apparatus to improve read latency of a multi-threshold level cell block-based non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method and apparatus to reduce read retry operations in a NAND Flash memory is provided. To reduce the number of read retries for future reads, a word line group is assigned an optimal read voltage, the reference voltage that results in eliminating the read error for the word line is selected as the optimal read voltage (also referred to as a “sticky voltage”) for the word line group to be used for a next read of the page. An optimal read voltage per word line group for the page per NAND Flash memory die is stored in the lookup table. Storing an optimal read voltage per word line group instead of per die reduces the number of read retries.”

The patent application was filed on 2019-09-27 (16/586214).

Firmware management of least recently used memory for cache hint optimization
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12141077) developed by Natarajan; Sriram, Folsom, CA, for a “firmware management of least recently used memory for cache hint optimization.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This application is directed to memory management in an electronic device. A memory includes a plurality of superblocks and receives a plurality of access requests. The electronic device stores information of an ordered list of superblocks in a cache, and each of a first subset of superblocks has a hint value and is ordered based on the hint value. In response to the plurality of access requests, the electronic device accumulates respective hint values of the first subset of superblocks and dynamically determines positions of the first subset of superblocks in the ordered list of superblocks based on the respective hint values of the first subset of superblocks. The ordered list of superblocks is pruned to generate a pruned list of superblocks. Based on the pruned list of superblocks, the electronic device converts a second subset of superblocks from a first memory type to a second memory type.”

The patent application was filed on 2023-06-08 (18/207570).

Dynamic program suspend disable for random write SSD workload
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12131064) developed by Angoth; Vivek, Longmont, CO, Carlton; David, Oakland, CA, Gangadhar; Sarvesh, Santa Clara, CA, Golez; MarkAnthony, Folsom, CA, Pelster; David J., Longmont, CO, and Vemula; Neelesh, Sunnyvale, CA, for a “dynamic program suspend disable for random write SSD workload.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An embodiment of an electronic apparatus may include one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to NAND-based storage media that includes a plurality of NAND devices, determine if a current workload for a particular NAND device of the plurality of NAND devices is a random write workload, and, if so determined, disable a program suspend operation for only the particular NAND device. Other embodiments are disclosed and claimed.”

The patent application was filed on 2021-04-27 (17/241976).

Utilizing multi-factor feedback control to allocate memory resources
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12131039) developed by Dreyer; David, Oronoco, MN, Chu; Henry, Rancho Cordova, CA, and Rodgers; Joey, Newcastle, CA, for “systems and methods for utilizing multi-factor feedback control to allocate memory resources.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method includes determining a write amplification factor for a particular NAND-based memory device and a host coupled to the NAND-based memory device and includes calculating a bandwidth of the host. Based on the write amplification factor and the bandwidth of the host, a resource of the NAND-based memory device is allocated between the host and a garbage collection process of the NAND-based memory device.”

The patent application was filed on 2023-04-05 (18/131286).

Dynamic management of memory read requests
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12118215) developed by Gangadhar; Sarvesh Varakabe, San Jose, CA, Golez; Mark Anthony, Folsom, CA, and Le; Jacky, Vancouver, Canada, for a “dynamic management of memory read requests.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This application is directed to dynamic management of memory read request in a memory system of an electronic device. The electronic device identifies a queue of memory access requests to access the memory system. The queue of memory access requests including at least one host read request and a current system read request. The electronic device monitors a workload condition of the memory system based on the queue of memory access requests, and generates at least a first system read request and a second system read request from the current system read request based on the workload condition of the memory system. The queue of memory access requests is updated by inserting the at least one host read request after the first system read request and before the second system read request.”

The patent application was filed on 2022-12-30 (18/092007).

Controlling memory overhead for storing integrity data in SSDs
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12118222) developed by Athreya; Arun, Zhang; Yihua, Natarajan; Shankar, and Natarajan; Sriram, Rancho Cordova, CA, for “controlling memory overhead for storing integrity data in solid state drives.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This application is directed to data protection in a memory system of an electronic device. The memory system has a first memory block and a second memory block, and each memory block includes one or more respective memory dies. Each memory die of the second memory block is distinct from the one or more respective memory dies of the first memory block. The electronic device stores user data including a plurality of user data items in the first memory block and integrity data including a plurality of integrity data items in the second memory block. Each of the plurality of user data items is configured to be validated based on a respective one of the plurality of integrity data items. The electronic device invalidates the integrity data in the second memory block, and reads the user data from the first memory block independently of the integrity data.”

The patent application was filed on 2023-02-23 (18/113495).

User configurable SLC memory size
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12093547) developed by Clark; Chace A., Hillsboro, OR, and Corrado; Francis, Redwood City, CA, for a “user configurable SLC memory size.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An embodiment of an electronic apparatus may include one or more substrates; and a controller coupled to the one or more substrates, the controller including logic to control access to a NAND-based storage media that includes a first cell region with a first number of levels and a second region with a second number of levels that is different from the first number of levels, determine logical block address locations that correspond to a user configurable capacity placeholder, and adjust respective sizes of the first cell region and the second cell region at runtime based on the logical block address locations. Other embodiments are disclosed and claimed.”

The patent application was filed on 2021-04-15 (17/231893).