Institute of Microelectronics Chinese Academy of Sciences Assigned Two Patents

Data recovery method for flash memory
Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China, has been assigned a patent (12197282) developed by Li; Qianhui, Wang; Qi, Yang; Liu, Jiang; Yiyang, Yu; Xiaolei, He; Jing, Huo; Zongliang, and Ye; Tianchun, Beijing, China, for a “data recovery method for flash memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A data recovery method for a flash memory includes: reading data from the flash memory by using preset read voltage; calculating a check node error rate corresponding to the data; calculating a read voltage adjustment step size according to the check node error rate; adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, and repeating the operation of calculating a check node error rate corresponding to the data to operation of adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, until the check node error rate is minimum; and selecting a read voltage corresponding to the minimum check node error rate to read data from the flash memory, so as to perform data recovery.”

The patent application was filed on 2021-04-08 (18/553929).

In-memory computing unit and in-memory computing circuit having reconfigurable logic
Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China, has been assigned a patent (12198746) developed by Cui; Yan, Luo; Jun, Yang; Meiyin, and Xu; Jing, Beijing, China, for “in-memory computing unit and in-memory computing circuit having reconfigurable logic.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An in-memory computing circuit having reconfigurable logic, including: an input stage and N output stages which are cascaded. The input stage includes 2.sup.N STT-MTJs. Each output stage includes STT-MTJs, of which a quantity is equal to a half of a quantity of STT-MTJs in a just previous stage. Two STT-MTJs in the previous stage and one STT-MTJ in the subsequent stage form a double-input single-output in-memory computing unit. Each double-input single-output in-memory computing unit can implement the four logical operations, i.e., NAND, NOR, AND, and OR, under different configurations. Data storage and logical operations can be realized under the same circuit architecture, and reconfigurations among different logic can be achieved.”

The patent application was filed on 2022-10-14 (17/966476).