OCP Global Summit 2024: Marvell Demos 3nm PCIe Gen 7 Connectivity for Accelerated Infrastructure

At OCP Global Summit 2024, Marvell Technology, Inc. demonstrates its 3nm PCIe Gen 7 connectivity.

PCIe Gen 7 doubles data transfer speeds, enabling continued scaling of compute fabrics inside accelerated server platforms, general-purpose servers, CXL systems and disaggregated infrastructure. Building on its widely deployed PAM4 technology and utilizing its accelerated infrastructure silicon platform, the company has developed the industry’s interconnect portfolio addressing all high-bandwidth optical and copper connections in AI data centers. This portfolio empowers cloud data center operators to optimize their infrastructure for their specific architectures and workloads to meet the exponential demands of AI.

The company pioneered PAM4 technology over a decade ago and leads the industry in PAM4 interconnect shipments. Today, most of the optical interconnects used in data center backend and frontend networks are based on PAM4 technology. As compared to PCIe Gen 5, which was based on NRZ modulation, PCIe Gen 6 and 7 require the use of PAM4 modulation. With its recent PCIe Gen 6 retimer announcement and this PCIe Gen 7 demonstration, the firm extends its PAM4-based optical and copper interconnect portfolio beyond Ethernet and IB into copper and optical PCIe, CXL and proprietary compute fabric links.

The increasing performance of processors and accelerators combined with the growing size of AI clusters is prompting the need for greater bandwidth speed and capacity. PCIe Gen 7 will enable larger volumes of data to be exchanged between processors to reduce the cost, time and energy required for training or inference. PCIe is the industry standard for inside-server-system connections between CPUs, GPUs, AI accelerators, and other server components. AI models are doubling their computation requirements every 6 months and are now the primary driver of the PCIe roadmap, with PCIe Gen 7 becoming a requirement.

“AI workloads are driving the evolution of server interconnects, and our PCIe Gen 7 technology is engineered to meet the performance and scalability needs of next-generation AI data centers,” said Venu Balasubramonian, VP, product marketing, connectivity business unit. “Our leadership in PAM4 SerDes technology in advanced process nodes enables us to deliver superior performance, low latency, and industry-leading performance, power and latency, providing a critical foundation for accelerated infrastructure.”

PCIe Gen 7, operating at 128GT/s per lane, enables AI and ML workloads to scale across compute fabrics. It delivers the high performance, low latency, and energy efficiency needed to power next-gen AI clusters, HPC systems, and cloud data centers.

The company’s PCIe Gen 7 SerDes is designed using 3nm fabrication technology enabling lower power consumption while delivering superior reach and link margins, that are critical for emerging AI super clusters. SerDes and parallel interconnects serve as high-speed pathways for exchanging data between chips. A rack in a hyperscale data center can contain up to tens of thousands of SerDes links.

Extending PAM4 leadership
Leveraging its PAM4 SerDes technology leadership and its data infrastructure IP, Marvell has created a connectivity platform that enables leading cloud data center operators to optimize their infrastructure for their unique architectures and workloads. In 2023, It introduced the Nova DSP, the industry’s 1st 1.6T PAM4 DSP. It has also introduced integrated PAM4 DSPs (Perseus) and DSPs optimized for efficiency (Spica Gen2-T) to serve the broadening spectrum of cloud data center link types and use cases. PAM4 technology is also the foundation of the Alaska A DSP chips optimized for active electrical cable (AEC) applications.