Neo Semiconductor Assigned Patent
Methods and apparatus for NAND flash memory
By Francis Pelletier | July 3, 2024 at 2:00 pmNEO Semiconductor, Inc., San Jose, CA, has been assigned a patent (11972811) developed by Hsu, Fu-Chang, San Jose, CA, for “methods and apparatus for NAND flash memory.“
The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a NAND flash memory is provided that includes a plurality of bit lines connected to a plurality of bit line select gates, respectively, and a page buffer connected to the plurality of bit line select gates. The NAND flash memory also includes a plurality of load devices connected to the plurality of bit lines, respectively. The plurality of load devices are configured to provide load current during read operations.”
The patent application was filed on 2021-08-26 (17/446165).