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Smart Modular Technologies CXL Add-in Cards for Memory Expansion in High Performance Servers

CXA-4F1W accommodates 4 DDR5 RDIMMs with maximum of 2TB of memory capacity when using 512GB RDIMMs, and CXA-8F2W accommodates 8 DDR5 RDIMMs with maximum of 4TB of memory capacity.

SMART Modular Technologies, Inc., a division of SGH (SMART Global Holdings, Inc.), announces its new family of Add-In Cards (AICs) which implements the Compute Express Link (CXL) standard and also supports industry standard DDR5 DIMMs.

Smart Modular Csl Aic 1These are a 1st in their class, high-density DIMM AICs to adopt the CXL protocol (*). The SMART 4-DIMM and 8-DIMM products enable server and data center architects to add up to 4TB of memory in a familiar, easy-to-deploy form factor.

Smart Modular Csl Aic Scheme2

The market for CXL memory components for data center applications is expected to grow rapidly. Initial production shipments are expected in late 2024 and will surpass the $2 billion mark by 2026. Ultimately, CXL attach rates in the server market will reach 30% including both expansion and pooling use cases,” stated Mike Howard, VP, DRAM and memory markets, TechInsights, an intelligence source to semiconductor innovation and related markets.

The CXL protocol is an important step toward achieving industry standard memory disaggregation and sharing which will significantly improve the way memory is deployed in the coming years,” said Andy Mills, senior director, advanced product development, SMART Modular, reinforcing Howard’s market analysis and SMART’s rationale for developing this family of CXL-related products.

CXA-4F1W 4-DIMM AIC

Smart Modular Cxa 4f1w 1

SMART’s 4-DIMM and 8-DIMM AICs are built using advanced CXL controllers which eliminate memory bandwidth bottlenecks and capacity constraints for compute-intensive workloads encountered in AI, HPC, and ML. These emerging applications require larger amounts of high-speed memory that exceed what current servers can accommodate. Attempts to add more memory via the traditional DIMM-based parallel bus interface is becoming problematic due to pin limitations on CPUs, so the industry is turning to CXL-based solutions which are more pin efficient.

CXA-8F2W 8-DIMM AIC

Smart Modular Cxa 8f2w 1

About SMART’s 4-DIMM and 8-DIMM DDR5 AICs

  • Available in type 3 PCIe Gen5 Full Height, Half Length (FHHL) PCIe form factor.

  • The 4-DIMM AIC (CXA-4F1W) accommodates 4 DDR5 RDIMMs with a maximum of 2TB of memory capacity when using 512GB RDIMMs, and the 8-DIMM AIC (CXA-8F2W) accommodates 8 DDR5 RDIMMs with a maximum of 4TB of memory capacity.

  • The 4-DIMM AIC uses a single CXL controller implementing 1×16 CXL port while the 8-DIMM AIC uses 2 CXL controllers to implement 2×8 ports, both resulting in a total bandwidth of 64GB/s.

  • The CXL controllers support ‘Reliability, Availability, and Serviceability’ (RAS) features, and advanced analytics.

  • Both offer enhanced security features with in-band or side band (SMBus) monitoring capability.

  • To accelerate memory processing, these add-in cards are compatible with SMART’s Zefr ZDIMMs.

CXL also enables lower cost scaling of memory capacity. Using Smart’s AICs enables servers to reach up to 1TB of memory per CPU with cost effective 64GB RDIMMs. They also offer an opportunity for supply chain optionality. Replacing high density RDIMMs with a greater number of lower density modules can enable lower system memory costs depending on market conditions.

Click to enlarge

Smart Modular Csl Aic Scheme

The company will provide samples to OEMs upon request. These CXL-based AIC products join firm’s ZDIMM line of DRAM as solutions for demanding memory design-in applications.

CXA-4F1W 4-DIMM AIC

Smart Cxa 4f1w Aic Face

Smart Cxa 4f1w Cxl Aic Spectabl

CXA-8F2W 8-DIMM AIC

Smart Cxa 8f2w Aic Face

Smart Modular Cxa 8f2w Aic Spectabl

Resources:
4-DIMM product page
8-DIMM AIC product page
CMM/CXL family page

(*) The CXL protocol is an important step toward achieving industry standard memory disaggregation and sharing which will significantly improve the way memory is deployed in the coming years.

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