Seagate Assigned Eleven Patents

Intelligent management of ferroelectric memory in storage device
Seagate Technology LLC, Fremont, CA, has been assigned a patent (11853213) developed by Trantham, Jon D., Chanhassen, MN, Viraraghavan, Praveen, Chicago, IL, Dykes, John W., Eden Prairie, MN, Gilbert, Ian J., Chanhassen, MN, Kalarickal, Sangita Shreedharan, Eden Prairie, MN, Totin, Matthew J., Excelsior, MN, El-Batal, Mohamad, Superior, CO, and Mehta, Darshana H., Shakopee, MN, for an “intelligent management of ferroelectric memory in a data storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Method and apparatus for managing a front-end cache formed of ferroelectric memory element (FME) cells. Prior to storage of writeback data associated with a pending write command from a client device, an intelligent cache manager circuit forwards a first status value indicative that sufficient capacity is available in the front-end cache for the writeback data. Non-requested speculative readback data previously transferred to the front-end cache from the main NVM memory store may be jettisoned to accommodate the writeback data. A second status value may be supplied to the client device if insufficient capacity is available to store the writeback data in the front-end cache, and a different, non-FME based cache may be used in such case. Mode select inputs can be supplied by the client device specify a particular quality of service level for the front-end cache, enabling selection of suitable writeback and speculative readback data processing strategies.”

The patent application was filed on 2022-04-27 (17/730920).

Asynchronous access multi-plane solid-state memory
Seagate Technology LLC, Fremont, CA, has been assigned a patent (11848055) developed by Goss, Ryan James, Prior Lake, MN, for an “asynchronous access multi-plane solid-state memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A solid-state memory may have many non-individually erasable memory cells arranged into dies with each die having a first plane and a second plane. Receipt of a single read command from a host connected to the solid-state memory can prompt generation of a first reference voltage and a second reference voltage by the controller to produce asynchronous data retrieval. The reference voltages can be different and selected by the controller to induce a predetermined delay between retrieval of data from the first plane and retrieval of data from the second plane from the single read command. Passage of each reference voltage concurrently to a common single data address of the first plane and the second plane may produce asynchronous retrieval of data from the respective first plane and second plane.”

The patent application was filed on 2021-08-19 (17/406346).

Semiconductor die failure recovery in storage device
Seagate Technology LLC, Fremont, CA, has been assigned a patent (11829270) developed by Secatch, Stacey, Niwot, CO, Perlmutter, Stephen H., Louisville, CO, Stoering, Matthew, Shakopee, MN, and Henze, Jonathan, Savage, MN, for a “semiconductor die failure recovery in a data storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Apparatus and method for a die kill and recovery sequence for a non-volatile memory (NVM). Data are stored in the NVM as data sets in garbage collection units (GCUs) that span multiple semiconductor dies. A die failure management circuit is configured to detect a die failure event associated with a selected die, and to generate a recovery strategy to accommodate the detected die failure event by selecting recovery actions to be taken in a selected sequence to maintain a current level of data transfer performance with a client device. The selected recovery actions are carried out in the selected sequence to transfer at least a portion of the user data stored in the selected die to a new replacement die, after which the selected die is decommissioned from further use. The NVM may be a flash memory of a solid-state drive (SSD).”

The patent application was filed on 2021-11-01 (17/516072).

Ordering reads to limit collisions in NVM
Seagate Technology LLC, Fremont, CA, has been assigned a patent (11822817) developed by Smith, Christopher, Fremont, CA, for “ordering reads to limit collisions in a non-volatile memory (NVM).“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). In some embodiments, a data storage device includes a main non-volatile memory (NVM), a host command queue that lists pending host read and host write commands, and a write cache which temporarily stores write data sets pending transfer to the NVM responsive to execution of the associated host write commands in the host command queue. A collision prediction circuit predicts a rate of future collisions involving the cached write data sets. A storage manager directs storage of the write data sets to a first target location responsive to the rate of future collisions being at a first level, and directs storage of the write data sets to a different, second target location responsive to the rate of future collisions being at a different, second level.”

The patent application was filed on 2021-07-27 (17/443554).

Solid-state memory with intelligent cell calibration
Seagate Technology LLC, Fremont, CA, has been assigned a patent (11810625) developed by Goss, Ryan J., Prior Lake, MN, Smith, Christopher A., Erie, CO, Zagade, Indrajit, Pune, India, and Henze, Jonathan, Savage, MN, for a “solid-state memory with intelligent cell calibration.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A solid-state memory may have many non-individually erasable memory cells arranged into calibration groups with each memory cell in each respective calibration group using a common set of read voltages to sense programmed states. An evaluation circuit of the solid-state memory may be configured to measure at least one read parameter for each calibration group responsive to read operations carried out upon the memory cells in the associated calibration group. An adjustment circuit of the solid-state memory may redistribute the memory cells of an existing calibration group into at least one new calibration group in response to the at least one measured read parameter.”

The patent application was filed on 2021-10-12 (17/499418).

Shape memory alloy based actuator latch
Seagate Technology LLC, Fremont, CA, has been assigned a patent (11783858) developed by Herdendorf, Brett R., Mound, MN, Mendonsa, Riyan Alex, Minneapolis, MN, and Subramanian, Krishnan, Shakopee, MN, for a “shape memory alloy based actuator latch.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A device disclosed herein includes an upper shape memory alloy (SMA) wire, a lower SMA wire, a flexure having an opening, and a spring configured within the flexure opening, wherein the lower SMA wire, and the flexure are attached at one end to an anchor and at another end to a pin.”

The patent application was filed on 2022-01-05 (17/569422).

SSD with printed circuit boards coupled by flexible interconnect
Seagate Technology LLC, Fremont, CA, has been assigned a patent (11755078) developed by Burski, Brian Lee, Loveland, CO, McDonald, Ted R, Louisville, CO, and Culver, Darrel R, Frederick, CO, for a “solid-state drive with printed circuit boards coupled by a flexible interconnect.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A solid-state drive (SSD) includes a first rigid printed circuit board comprising a surface that defines a first plane. A second rigid printed circuit board of the SSD comprises a surface that defines a second plane that is substantially parallel to the first plane. A flexible interconnect couples the first rigid printed circuit board and the second rigid printed circuit board. The flexible interconnect partially encloses a volume. A capacitor is disposed within the volume.”

The patent application was filed on 2021-06-22 (17/354938).

Coarse interleaving
Seagate Technology LLC, Fremont, CA, has been assigned a patent (11757472) developed by Patapoutian, Ara, Rancho Santa Fe, CA, Jury, Jason Charles, Apple Valley, MN, Sridhara, Deepak, Longmont, CO, and Bellorado, Jason, San Jose, CA, for a “coarse interleaving.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method includes encoding a sector of data to be written to a data storage device with a single error correcting code (ECC). The sector of data is divided into N individually readable and writeable portions, with N≥2. The individually readable and writeable portions of the sector of data are separated with a space between the portions of the sector of data in a pattern.”

The patent application was filed on 2022-05-16 (17/744874).

Client I/O access rate variation compensation
Seagate Technology LLC, Fremont, CA, has been assigned a patent (11748277) developed by Goss, Ryan James, Prior Lake, MN, Claude, David W., Loveland, CO, Ferris, Graham David, Benjamin, Daniel John, Savage, MN, and Weidemann, Ryan Charles, Victoria, MN, for a “client input/output (I/O) access rate variation compensation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Method and apparatus for enhancing performance of a storage device, such as a solid-state drive (SSD). In some embodiments, the storage device monitors a rate at which client I/O access commands are received from a client to transfer data with a non-volatile memory (NVM) of the storage device. A ratio of background access commands to the client I/O access commands is adjusted to maintain completion rates of the client I/O access commands at a predetermined level. The background access commands transfer data internally with the NVM to prepare the storage device to service the client I/O access commands, and can include internal reads and writes to carry out garbage collection and metadata map updates. The ratio may be adjusted by identifying a workload type subjected to the storage device by the client.”

The patent application was filed on 2020-03-05 (16/810357).

Coalescing read commands by location from host queue
Seagate Technology LLC, Fremont, CA, has been assigned a patent (11698754) developed by McJilton, Charles, Longmont, CO, Pream, Jeffrey, Berthoud, CO, Henze, Jonathan, Savage, MN, and Zagade, Indrajit, Maharashtra, India, for “coalescing read commands by location from a host queue.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). A non-volatile memory (NVM) is arranged into multiple garbage collection units (GCUs) each separately erasable and allocatable as a unit. Read circuitry applies read voltages to memory cells in the GCUs to sense a programmed state of the memory cells. Calibration circuitry groups different memory cells from different GCUs into calibration groups that share a selected set of read voltages. A read command queue accumulates pending read commands to transfer data from the NVM to a local read buffer. Read command coalescing circuitry coalesces selected read commands from the queue into a combined command for execution as a single batch command. The combined batch command may include read voltages for use in retrieval of the requested data.”

The patent application was filed on 2021-10-04 (17/492918).

Pre-emptive storage strategies to reduce host command collisions
Seagate Technology LLC, Fremont, CA, has been assigned a patent (11693596) developed by Pream, Jeffrey J., Berthoud, CO, for “pre-emptive storage strategies to reduce host command collisions.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). A data storage device includes a main non-volatile memory (NVM) and a command queue that lists pending data transfer commands to transfer data between the NVM and a local memory. A collision manager predicts future collisions among the pending data transfer commands, such as but not limited to commands involving pending host commands from a host. A storage manager enacts a change in a storage policy to reduce a future rate of the predicted future collisions. The change in storage policy may involve duplication of write data so that the write data are written to multiple locations within the NVM. The change in storage policy may further involve a pre-emptive garbage collection operation upon an existing location to distribute current version data blocks to multiple locations within the NVM.”

The patent application was filed on 2021-07-30 (17/389856).