R&D: Exploiting Single-Symbol LLR Variation to Accelerate LDPC Decoding for 3D NAND Flash Memory

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems has published an article written by Yingge Li, Guojun Han, Chang Liu, School of Information Engineering, Guangdong University of Technology, Guangzhou, China, Meng Zhang, School of Computer Science and Technology, Huazhong University of Science and Technology, Wuhan, China, and Fei Wu, Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan, China

Abstract: “Low-density parity-check (LDPC) codes have been widely adopted to guarantee data reliability in 3-D NAND flash memory. However, the iterative LDPC decoding algorithm leads to high decoding latency due to the iterative message transfer mechanism. Using a field-programmable gate array (FPGA) testbed, we first present the binary channel in NAND flash and analyze the single-symbol log-likelihood ratio (LLR) variation with the decoding iterations. Subsequently, we investigate the raw bit error ratio (RBER) characteristics of intra-page frames. To reduce the number of iterative decoding, we propose a frame feedback information aware decoding algorithm (FFIA-DA), combined with the single-symbol LLR variation and the similar error characteristics among intra-page frames. The proposed method uses the decoding feedback information of one frame to decrease the number of decoding iterations of other frames with similar RBER. Experiments show that the proposed approach can improve the decoding performance of LDPC and speed up decoding convergence.“