Western Digital Technologies Assigned Fifteen Patents

Magnetic head with assisted magnetic recording
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11682419) developed by Kuroki, Kenji, Fujisawa, Japan, Ruiz, Oscar, Hwang, Cherngye, and Torres Mireles, Eduardo, San Jose, CA, for a “magnetic head with assisted magnetic recording.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A magnetic recording head assembly is provided and is configured to read from and write to a magnetic media. The head assembly includes a first module having a first media facing surface (MFS), a first closure, and a first recessed portion disposed between the first MFS and the first closure. The first MFS includes AlTiC. A second module is provided having a second MFS, a second closure, and a second recessed portion disposed between the second MFS and the second closure. The second MFS includes AlTiC. An overcoat disposed within the first and second recessed portions includes an adhesive layer and a protective layer disposed within the first and second recessed portion.”

The patent application was filed on 2021-08-13 (17/401846).

Asymmetric write head shields compatible with dual-free-layer (DFL) readers
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11682417) developed by Lam, Quan-Chiu Harry, San Jose, CA, for “asymmetric write head shields compatible with dual-free-layer (DFL) readers.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure is generally directed towards magnetic recording systems comprising a dual free layer (DFL) read head and a magnetic recording head having stable magnetization. The magnetic recording head comprises a main pole disposed at a media facing surface (MFS), and a plurality of shields, such as a lower leading shield, an upper leading shield, a pair of side shields, and a trailing shield. Each of the shields individually comprises a first leg disposed at and parallel to the MFS and a second leg coupled to the first leg, the second leg being recessed from the MFS. When the kind of magnetization initialization needed by the DFL read head is applied to the magnetic recording head during the manufacturing process, the second leg of each of the shields of the magnetic recording device causes the magnetization directions of the shields to individually switch to a stable state.”

The patent application was filed on 2022-05-09 (17/740293).

Data integrity protection with partial updates
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11681581) developed by Ilani, Ishai, Dolev, Israel, Zamir, Ran, Ramat Gan, Israel, Inbar, Karin, Ramat Hasharon, Israel, Sharon, Eran, Rishon Lezion, Israel, and Alrod, Idan, Herzliya, Israel, for a “data integrity protection with partial updates.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Effective use of cyclic redundancy check (CRC) signatures is achieved where each sector of a flash management unit (FMU) has a distinct CRC signature. The CRC signatures are XORed together to create a total CRC signature for the FMU. When a host device updates a single sector of the FMU, the CRC signature for the updated single sector can be changed by removing the old CRC signature corresponding to the single sector and replacing the old CRC signature with a new CRC signature corresponding to the updated single sector. The old CRC signature is XORed from the total CRC signature and then the new CRC signature is XORed with the remaining CRC signatures to create a new total CRC signature. In so doing, data integrity is ensured.”

The patent application was filed on 2022-06-21 (17/845770).

Parallel model deployment for AI using primary storage system
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11676066) developed by Sarkar, Sanhita, Fremont, CA, for a “parallel model deployment for artificial intelligence using a primary storage system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Example artificial intelligence systems and methods provide parallel storage of data to primary storage and notification to a model server supported by the primary storage. A primary storage system receives operations on a training data set from a model trainer and sends a model instance of a computational model to a model server. When a new data element is received by a data ingester, the model server is initiated to evaluate the new data element using the model instance while the primary storage system stores the new data element in parallel.”

The patent application was filed on 2020-01-17 (16/746381).

Synchronous discovery logs in fabric storage system
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11675499) developed by Dhatchinamoorthy, Rahul Gandhi, and Ranjan, Kumar, Bangalore, India, for “synchronous discovery logs in a fabric storage system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems and methods for distributed storage systems using synchronous discovery logs for fabric subsystem discovery. Storage nodes may be configured with fabric services and a management service may provide synchronization of discovery logs across fabric subsystems and between peer fabric nodes. The peer fabric nodes may communicate with one another using a fabric network protocol and corresponding fabric subsystems may communicate with each peer fabric node. When a target subsystem fabric node updates its discovery log, the updated discovery log is sent to the corresponding peer fabric node. The corresponding peer fabric node sends the updated discovery log to each subsystem fabric node and to each peer fabric node for synchronization across all subsystem fabric nodes. A host may contact any subsystem fabric node for the updated discovery log.”

The patent application was filed on 2020-06-19 (16/906404).

Devices and methods for failure detection and recovery for distributed cache
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11675706) developed by Radi, Marjan, and Vucinic, Dejan, San Jose, CA, for “devices and methods for failure detection and recovery for a distributed cache.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A programmable switch includes at least one memory configured to store a cache directory for a distributed cache, and circuitry configured to receive a cache line request from a client device to obtain a cache line. The cache directory is updated based on the received cache line request, and the cache line request is sent to a memory device to obtain the requested cache line. An indication of the cache directory update is sent to a controller for the distributed cache to update a global cache directory. In one aspect, the controller sends at least one additional indication of the update to at least one other programmable switch to update at least one backup cache directory stored at the at least one other programmable switch.”

The patent application was filed on 2020-06-30 (16/916730).

Switch based BGA extension
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11675528) developed by Yadav, Akhilesh, Muthiah, Ramanathan, and Peter, Eldhose, Karnataka, India, for a “switch based BGA extension.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Aspects of a storage device including a memory and a controller are provided. The memory includes a plurality of non-volatile memory packages coupled to the switch, in which each non-volatile memory package includes a plurality of non-volatile memory dies. The controller can select a non-volatile memory package with the switch. The controller can establish a data channel connection between the selected non-volatile memory package and the controller via the switch. In some aspects, the selected non-volatile memory package is transitioned into an active mode and one or more non-selected non-volatile memory packages are each transitioned into a standby mode. The controller also can perform one or more storage device operations with one or more non-volatile memory dies of the plurality of non-volatile memory dies within the selected non-volatile memory package. Thus, the controller may facilitate a switch based ball grid array extension, thereby improving memory capacity of the storage device.”

The patent application was filed on 2021-03-29 (17/216046).

Magnetic recording head with stable magnetization of shields
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11676627) developed by Lam, Quan-Chiu Harry, San Jose, CA, for a “magnetic recording head with stable magnetization of shields.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Aspects of the present disclosure generally relate to a magnetic recording head that includes a main pole, a leading shield, a first side shield disposed on a first side of the main pole, a second side shield disposed on a second side of the main pole, and a trailing shield. The trailing shield is disposed on a trailing side of the main pole. One or more approaches are disclosed to control return-fluxes. In some embodiments, at least one of the upper return pole, the leading shield, the trailing shield, the first side shield, and the second side shield includes a laminate structure having at least a pair of ferromagnetic layers, and a non-magnetic spacer layer disposed between adjacent ferromagnetic layers. In some embodiments, one or more shunts are positioned, such as connecting the leading shield to the upper return pole in order to create circuits to control magnetic flux.”

The patent application was filed on 2021-08-06 (17/396234).

Multiple-portion hard disk drive slider pad configuration
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11676628) developed by Naka, Kohichiroh, Fujisawa, Japan, Hyugano, Takeshi, Toshima, Japan, Murata, Kenichi, Ebina, Japan, and Matsumoto, Yuhsuke, Fujisawa, Japan, for a “multiple-portion hard disk drive slider pad configuration.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A hard disk drive head slider housing a read-write transducer includes a plurality of electrical connection pads, where each electrical pad includes an interconnection portion configured for electrically connecting to an interconnected component, such as a lead suspension, a probe contact portion configured for electrical testing the head slider, and at least one slit positioned between the interconnection portion and the probe contact portion, thereby physically distinguishing and separating the two portions of a multiple-portion pad to inhibit undesirable solder flow to the wider probe contact portion on the slider side of each pad. A more controlled solder joint is provided, while the probe contact portion can remain relatively wide for probe contact and the interconnection portion can remain relatively narrow to reduce solder bridges among the pads.”

The patent application was filed on 2021-12-02 (17/541219).

Externalizing inter-symbol interference data in data channel
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11677420) developed by Galbraith, Richard, Rochester, MN, Goode, Jonas, Lake Forest, CA, Oboukhov, Louri, and Ravindran, Niranjay, Rochester, MN, for “externalizing inter-symbol interference data in a data channel.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Example systems, read channel circuits, data storage devices, and methods to use inter-symbol interference message passing (ISI-MP) data in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, configured to determine both the first most likely and second most likely sets of symbols and output inter-symbol interference data based on the adjacent symbols and corresponding ISI in each set of symbols. The inter-symbol interference data may be used by an ISI-MP circuit configured to model ISI-MP and provide feedback to an iterative decoder during local iterations.”

The patent application was filed on 2022-03-01 (17/683958).

Servo writer head design for rotated servo pattern
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11676630) developed by Yamamoto, Satoshi, San Jose, and Kobayashi, Masahito, Fujisawa, Japan, for a “servo writer head design for the rotated servo pattern.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure is generally related to a servo track writer (STW) head for writing a rotated servo pattern. The STW head comprises a first writer stripe having a first length tilted at a first angle and a second writer stripe having a second length tilted at a second angle. The STW head may be tilted at a non-perpendicular angle relative to the edge of a tape configured to pass under the STW head.”

The patent application was filed on 2022-02-15 (17/651117).

Completion entry throttling using host memory
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11669267) developed by Benisty, Shay, Beer Shiva, Israel, for a “completion entry throttling using host memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Technologies and techniques for use by a data storage controller or similar device for throttling the delivery of completion entries pertaining to the execution of commands by a nonvolatile memory (NVM) device are provided. In an illustrative example, the data storage controller selectively throttles the delivery of completion entries to a host device using uniform delivery intervals to provide for stable delivery of completion entries to the host. In some examples, the throttling is achieved by storing new completion entries in a completion queue of the host while initially setting corresponding indicator bits within the completion entries (e.g. phase tags) to cause the host to ignore the new completion entries as though the new entries were old entries. Later, after a throttling delay interval, the indicator bits are inverted to allow the host to recognize and process the new completion entries. NVMe examples are provided.”

The patent application was filed on 2020-06-29 (16/915981).

Processing problematic signal modulation patterns as erasures using wireless communication devices
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11671198) developed by Galbraith, Richard Leo, Oboukhov, Iouri, Rochester, MN, and Goode, Jonas Andrew, Lake Forest, CA, for “processing problematic signal modulation patterns as erasures using wireless communication devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods and apparatus are provided for controlling wireless signal transmissions, wherein problematic symbol patterns are relocated to an erasure region of a data packet prior to erasure encoding and transmission. Relocating the problematic symbol patterns is done so that, when the resulting erasure codeword is punctured and transmitted, the problematic patterns are not transmitted. Yet, those patterns can be restored by the decoder at the receiving device using an erasure decoder in accordance with erasure decoding techniques, e.g., punctured low-density parity-check (LDPC) decoding techniques. In this manner, problematic symbol patterns that may be corrupting during transmission due to noise are removed (punctured) prior to transmission, then restored by the decoder during decoding.”

The patent application was filed on 2021-09-14 (17/474345).

Storage capacity recovery source selection
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11663136) developed by Xie, Hongmei, Gorrle, Dhanunjaya Rao, Milpitas, CA, and Karki, Aajna, San Jose, CA, for a “storage capacity recovery source selection.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory device includes a volatile memory, a non-volatile memory, and a controller. The controller is configured to map logical addresses for stored data to physical addresses of the stored data in the non-volatile memory using a logical-to-physical mapping structure stored partially in the volatile memory and at least partially in the non-volatile memory. The controller is configured to perform a storage capacity recovery operation for a region of the non-volatile memory that is selected based at least partially on a number of mappings for the region likely to be stored in the volatile memory for the storage capacity recovery operation.”

The patent application was filed on 2020-06-24 (16/910973).

Write abort error detection in multi-pass programming
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11663068) developed by Banerjee, Amiya, and Bhat, Vinayak, Bangalore, India, for a “write abort error detection in multi-pass programming.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage device may detect errors during data transfer. Upon detection of one or more data transfer errors, for example, the storage device can begin to scan pages within a plurality of memory devices for uncorrectable error correction codes. Once scanned, a range of pages within the plurality of memory devices with uncorrectable error correction codes associated with a write abort error may be determined. The stage of multi-pass programming achieved on each page within that range is then established. Once calculated, the previously aborted multi-pass programming of each page within the range of pages can continue until completion. Upon completion, normal operations may continue without discarding physical data location.”

The patent application was filed on 2020-06-29 (16/915617).