STMicroelectronics Assigned Three Patents

Phase change memory, system and method for operating memory device
STMicroelectronics, Inc., Coppell, TX, and STMicroelectronics S.r.l., Agrate Brianza, Italy, has been assigned a patent (11756614) developed by Perroni, Maurizio Francesco, Messina, Italy, Disegni, Fabio Enrico Carlo, Spino d’adda, Italy, Manfré, Davide, Pandino, Italy, and Torti, Cesare, Pavia, Italy, for “phase change memory device, system including the memory device, and method for operating the memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A phase-change memory device column decoder is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.”

The patent application was filed on 2022-04-04 (17/657861).

Memory device and method for in-memory computing
STMicroelectronics, Inc., Coppell, TX, and STMicroelectronics S.r.l., Agrate Brianza, Italy, has been assigned a patent (11756615) developed by Carissimi, Marcella, Treviolo, Italy, Pasotti, Marco, Travaco′ Siccomario, Italy, and Canegallo, Roberto Antonio, Rimini, Italy, for “memory device and method for in-memory computing.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An embodiment memory device comprises a plurality of memory cells, each exhibiting a transconductance depending on a value of a stored bit, a plurality of bit lines associated with respective groups of memory cells, each bit line configured to flow a respective electric current indicative of the bit stored in a selected memory cell of the respective group of memory cells, and a computing circuit providing an output electric quantity indicative of a linear combination of a plurality of input electric quantities. The computing circuit comprises a biasing stage configured to bias each bit line with a respective input electric quantity, the electric current flowing through each bit line based on a product of the respective input electric quantity and the transconductance of the selected memory cell, and a combining stage for combining the electric currents flowing through the plurality of bit lines thereby obtaining the output electric quantity.”

The patent application was filed on 2021-08-31 (17/462250).

SRAM cell layout including arrangement of multiple active regions and multiple gate regions
STMicroelectronics, Inc., Coppell, TX, and STMicroelectronics S.r.l., Agrate Brianza, Italy, has been assigned a patent (11758707) developed by Ahmed, Shafquat Jahan, Greater Noida, India, and Dhori, Kedar Janardan, Ghaziabad, India, for a “SRAM cell layout including arrangement of multiple active regions and multiple gate regions.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory cell including a set of active regions that overlay a set of gate regions to form a pair of cross-coupled inverters. A first active region extends along a first axis. A first gate region extends transversely to the first active region and overlays the first active region to form a first transistor of the pair of cross-coupled inverters. A second gate region extends transversely to the first active region and overlays the first active region to form a second transistor of the pair of cross-coupled inverters. A second active region extends along a second axis and overlays the first gate region to form a third transistor of the pair of cross-coupled inverters. A fourth active region extending along a third axis and overlays a gate region to form a transistor of a read port.”

The patent application was filed on 2020-12-10 (17/118372).