R&D: In-memory Neural Network Accelerator Based on PCM with One-Selector/One-Resistor Structure Operated in Subthreshold Regime

2023 IEEE International Memory Workshop (IMW) has published an article written by N. Lepri, P. Gibertini, P. Mannocci, Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Politecnico di Milano and IU.NET Piazza L. da Vinci 32, Milano (MI), Italy, A. Pirovano, I. Tortorelli, P. Fantini, Micron Technology Inc., Via Trento 26, Vimercate (MB), Italy, and D. Ielmini, Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Politecnico di Milano and IU.NET Piazza L. da Vinci 32, Milano (MI), Italy.

Abstract: “In-memory computing (IMC) shows a disruptive potential for accelerating artificial intelligence (AI) in both inference and training tasks. Scalable IMC, however, requires novel memory technologies with extremely low current. Here we demonstrate ultra-low current matrix-vector multiplication (MVM) in a crosspoint array of phase change memory (PCM) and ovonic threshold switch (OTS) with one-selector/one-resistor (181R) structure operated in the subthreshold regime. Thanks to highly-uniform sub-μA currents, the 181R PCM crosspoint array rejects parasitic IR drop across wires, enabling excellent scaling compared to other memory devices. Our simulation of a fullyconnected neural network (FCNN) with ternary weights indicates an accuracy of 98% for MNIST classification with an array size of 512×512, which strongly supports subthreshold-operated 181R crosspoint arrays for neural network inference accelerators.“