R&D: Effect of High-Temperature Bake on RTN Statistics in Floating Gate Flash Memory Arrays

2023 IEEE International Memory Workshop (IMW) has published an article written by Viktor Markov, Silicon Storage Technology, Inc., a subsidiary of Microchip Technology, Inc., San Jose, CA, USA, Gilles Festes, Silicon Storage Technology, Inc., a subsidiary of Microchip Technology, Inc., Rousset, France, Louisa Schneider, Steven Lemke, Silicon Storage Technology, Inc., a subsidiary of Microchip Technology, Inc., San Jose, CA, USA, Serguei Jourba, Silicon Storage Technology, Inc., a subsidiary of Microchip Technology, Inc., Rousset, France, and Alexander Kotov, Silicon Storage Technology, Inc., a subsidiary of Microchip Technology, Inc., San Jose, CA, USA.

Abstract: “The impact of high-temperature (HT) bake on random telegraph noise (RTN) statistics in floating gate (FG) flash memory arrays was studied. It was found that HT bake of the memory array set in erase state can effectively suppress RTN previously induced by HT bake of the memory array set in program state. Since program and erase states are characterized by negatively and positively charged FG respectively, the FG potential plays a crucial role in the direction of the RTN intensification or alleviation. The effect of HT bake on RTN was extensively analyzed as a function of the FG potential, bake temperature, and bake duration. By alternating HT bakes of the memory arrays in program and erase states, we observed a reversible switching of the RTN traps between active and inactive modes. This behavior suggests that the RTN traps in our biastemperature stress experiments were not newly generated but rather originated ones from the pre-existed defect precursors in FG oxide.“