R&D: DNN-Based Error Level Prediction for Reducing Read Latency in 3D NAND Flash Memory

Microelectronics Reliability has published an article written by Jing He, Xiaolei Yu, Qianhui Li, Bo Zhang, Xianliang Wang, Qianqi Zhao, Xuhong Qiang, Qi Wang, nstitute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China, and University of Chinese Academy of Sciences, Beijing 100049, China, Zongliang Huo, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China, and University of Chinese Academy of Sciences, Beijing 100049, China, and Yangtze Memory Technology Co., Ltd., Wuhan 430205, China, and Tianchun Ye, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China, and University of Chinese Academy of Sciences, Beijing 100049, China.

Abstract: “3D NAND Flash memory still suffers from many reliability issues in practice, such as endurance and data retention errors. Meanwhile, due to process variation, pages with different layers show different error characteristics even in the same block. In this paper, we firstly propose a deep neural network-based codeword error level prediction model that can effectively predict the level of codeword errors, and we consider all the main factors that affect the codeword errors, including the P/E cycles and retention time, the location information of the codeword. The new network structure can effectively reduce the weight size by approximately 27% without loss of accuracy compared to traditional neural network. Based on this prediction model, we further propose an optimized scheme to reduce the read latency of the system. The results of the model prediction can help the controller to choose a suitable decoding scheme, thus reducing the overall read latency. Experiments show that the proposed network can predict the error level of the codeword to over 97% accuracy, and also significantly help to improve the average read performance with a maximum latency reduction of 45.3%.“