STMicroelectronics Assigned Three Patents

Writing electrically erasable and programmable NVM and corresponding integrated circuit
STMicroelectronics (Rousset) SAS, Rousset, France, has been assigned a patent (11670385) developed byTailliet, François, Fuveau, france, and Ameziane El Hassani, Chama, Aix en Provence, France, for “method for writing an electrically erasable and programmable non volatile memory and corresponding integrated circuit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for writing to electrically erasable and programmable non-volatile memory and a corresponding integrated circuit are disclosed. In an embodiment a method includes operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, generating, by the oscillator circuit, an oscillation signal and regulating the oscillation signal by the filter circuit so as to generate a clock signal for timing a write cycle.”

The patent application was filed on 2021-12-21 (17/558123).

Chip containing onboard NVM comprising phase-change material
STMicroelectronics (Crolles 2) SAS, Crolles, France, STMicroelectronics (Grenoble 2) SAS, Grenoble, France, and STMicroelectronics (Rousset) SAS, Rousset, France, has been assigned a patent (11653582) developed by Arnaud, Franck, St. Nazaire les Eymes, France, Galpin, David, Le Cheylas, France, Zoll, Stephane, Froges, France, Hinsinger, Olivier, Barraux, France, Favennec, Laurent, Villard, Bonnot, France, Oddou, Jean-Pierre, Saint-Ismier, France, Broussous, Lucile, Goncelin, France, Boivin, Philippe, Venelles, France, Weber, Olivier, Grenoble, France, Brun, Philippe, Meylan, France, and Morin, Pierre, Kessel-Lo, Belgium, for a “chip containing an onboard non-volatile memory comprising a phase-change material.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.”

The patent application was filed on 2018-11-08 (16/184246).

Integrity check of memory
STMicroelectronics (Grenoble 2) SAS, Grenoble, France, has been assigned a patent (11650738) developed by Briat, Gerald, Vif, France, and Marmey, Stephane, Fontanil, France, for an “integrity check of a memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The integrity of a memory is checked by: storing data representative of an operation to be executed in the memory, executing the operation, and erasing the data once the execution is complete.”

The patent application was filed on 2020-12-04 (17/111778).