Fungible/Microsoft Assigned Six Patents

Data flow graph-driven analytics platform using data processing units having hardware accelerators
Fungible, Inc., Santa Clara, CA, (acquired by Microsoft Corp.) has been assigned a patent (11636154) developed by Goyal, Rajan, Saratoga, CA, and Billa, Satyanarayana Lakshmipathi, Sunnyvale, CA, for “data flow graph-driven analytics platform using data processing units having hardware accelerators.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A data flow graph-driven analytics platform is described in which highly-programmable data stream processing devices, referred to generally herein as data processing units (DPUs), operate to provide a scalable, fast and efficient analytics processing architecture. In general, the DPUs are specialized data-centric processors architected for efficiently applying data manipulation operations (e.g., regular expression operations to match patterns, filtering operations, data retrieval, compression/decompression and encryption/decryption) to streams of data units, such as packet flows having network packets, a set of storage packets being retrieved from or written to storage or other data units.”

The patent application was filed on 2019-09-26 (16/584293).

Query processing using data processing units having DFA/NFA hardware accelerators
Fungible, Inc., Santa Clara, CA, (acquired by Microsoft Corp.), has been assigned a patent (11636115) developed by Billa, Satyanarayana Lakshmipathi, Sunnyvale, CA, for “query processing using data processing units having DFA/NFA hardware accelerators.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A system comprises a data source storing data, a data processing unit (DPU) comprising an integrated circuit having programmable processor cores and a hardware-based regular expression (RegEx) engine, and a control node configured to generate a data flow graph for configuring the DPUs to execute the analytical operation to be performed on the data. The analytical operation specifies a query having at least one query predicate. A controller is configured to receive the data flow graph and, in response, configures the DPU to input the data as one or more data streams, and configure the RegEx engine to operate according to one or more deterministic finite automata (DFAs) or non-deterministic finite automata (NFAs) to evaluate the query predicate against the data by applying one or more regular expressions to the one or more data streams.”

The patent application was filed on 2019-09-26 (16/584467).

Scaled-out transport as connection proxy for device-to-device communications
Fungible, Inc., Santa Clara, CA, (acquired by Microsoft Corp.), has been assigned a patent (11637773) developed by Noureddine, Wael, Santa Clara, CA, Marti, Felix A., San Francisco, CA, Zhou, Aibing, San Jose, CA, Budko, Dmitriy Leonidovich, Los Altos, CA, Gupte, Gaurav, San Jose, CA, Tran, Hoai Vu Thanh, Gilroy, CA, Lappasi, Aravind Vidhyasagar, Austin, TX, Leedom, Leith Alan, Palo Alto, CA, and Nair, Rajesh G., Fremont, CA, for a “scaled-out transport as connection proxy for device-to-device communications.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Techniques are described for providing a scaled-out transport supported by interconnected data processing units (DPUs) that operates as a single system bus connection proxy for device-to-device communications within a data center. As one example, this disclosure describes techniques for providing a Peripheral Component Interconnect Express (PCIe) proxy for device-to-device communications employing the PCIe standard. The disclosed techniques include adding PCIe proxy logic on top of a host unit of a DPU to expose a PCIe proxy model to application processors, storage devices, network interface controllers, field programmable gate arrays, or other PCIe endpoint devices. The PCIe proxy model may be implemented as a physically distributed Ethernet-based switch fabric with PCIe proxy logic at the edge and fronting the PCIe endpoint devices. The interconnected DPUs and the distributed Ethernet-based switch fabric together provide a reliable, low-latency, and scaled-out transport that operates as a PCIe proxy.”

The patent application was filed on 2021-02-09 (17/248828).

Reliability coding with reduced network traffic
Fungible, Inc., Santa Clara, CA, (acquired by Microsoft Corp.), has been assigned a patent (11630729) developed by Menon, Jaishankar, Saratoga, Sindhu, Pradeep, Los Altos Hills, CA, and Vaka, Pratapa Reddy, Saratoga, CA, for a “reliability coding with reduced network traffic.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This disclosure describes techniques that include implementing network-efficient data durability or data reliability coding on a network. In one example, this disclosure describes a method that includes generating a plurality of data fragments from a set of data to enable reconstruction of the set of data from a subset of the plurality of data fragments, storing, across a plurality of nodes in a network, the plurality of data fragments, wherein storing the plurality of data fragments includes storing the first fragment at a first node and the second fragment at a second node, and generating, by the first node, a plurality of secondary fragments derived from the first fragment to enable reconstruction of the first fragment from a subset of the plurality of secondary fragments, and storing the plurality of secondary fragments from the first fragment across a plurality of storage devices included within the first node.”

The patent application was filed on 2021-04-26 (17/302173).

Pipeline using match-action blocks
Fungible, Inc., Santa Clara, CA, (acquired by Microsoft Corp.), has been assigned a patent (11579802) developed by Thantry, Hariharan Lakshminarayanan, Fremont, CA, Vegesna, Srihari Raju, Nedunchezhian, Sureshkumar, and Oak, Stimit Kishor, San Jose, CA, for a “pipeline using match-action blocks.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An apparatus includes an output bus configured to store data, a match table, one or more storage devices, and logic. The match table is configured to store a plurality of entries, each entry including a key value, wherein the match table specifies a matching entry in response to being queried by the query data. The one or more storage devices are configured to store operation information for each of the plurality of entries stored in the match table. The operation information specifies one or more instructions associated with each respective entry in the plurality of entries stored in the match table. The logic is configured to receive one or more operands from the output bus, identify one or more instructions from the one or more storage devices, and generate, based on the one or more instructions and the one or more operands, processed data.”

The patent application was filed on 2020-10-02 (17/061725).

Efficient packet queueing for computer networks
Fungible, Inc., Santa Clara, CA, (acquired by Microsoft Corp.), has been assigned a patent (11552907) developed by Kim, Paul, Fremont, CA, and Thomas, Philip A., San Jose, CA, for an “efficient packet queueing for computer networks.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method during a first cycle includes receiving, at a first port of a device, a plurality of network packets. The method may include storing, by the device, at least some portion of a first packet of the plurality of network packets at a first address within a first record bank and storing, by the device and concurrent with storing the at least some portion of the first packet from the first address, at least some portion of a second packet of the plurality of network packets at a second address within a second record bank, different than the first record bank. The method may further include storing, by the device, the first address within the first record bank and the second address within the second record bank in the first link stash associated with the first record bank and updating, by the device, a tail pointer to reference the second address.”

The patent application was filed on 2020-08-14 (16/947754).