Ememory Technology Assigned Two Patents

One time programmable NVM cell on glass substrate
Ememory Technology Inc., Hsin-Chu, TaiwanY, has been assigned a patent (11610103) developed by Sun, Wein-Town, and Hsiao, Woan-Yun, Hsinchu County, Taiwan, for an “one time programmable non-volatile memory cell on glass substrate.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A one time programmable non-volatile memory cell includes a storage element. The storage element includes a glass substrate, a buffer layer, a polysilicon layer and a metal layer. The buffer layer is disposed on the glass substrate. The polysilicon layer is disposed on the buffer layer. A P-type doped region and an N-type doped region are formed in the polysilicon layer. The metal layer is contacted with the N-type doped region and the P-type doped region. The metal layer, the N-type doped region and the P-type doped region are collaboratively formed as a diode. When a program action is performed, the first diode is reverse-biased, and the diode is switched from a first storage state to a second storage state. When a read action is performed, the diode is reverse-biased and the diode generates a read current.”

The patent application was filed on 2021-01-19 (17/151774).

Memory for improving weak-program or stuck bit
Ememory Technology Inc., Hsin-Chu, TaiwanY, has been assigned a patent (11605438) developed by Su, Ting-Ting, Hsinchu County, Taiwan, for a “memory device for improving weak-program or stuck bit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Provided is a memory device including a memory structure including a substrate, a channel region, first and second doped regions, a floating gate and a dielectric layer. The channel region is disposed on the substrate. The first and the second doped regions are disposed on the substrate and respectively located at two sides of the channel region. The floating gate is disposed on the channel region. The dielectric layer is disposed between the floating gate and the channel region, the first doped region and the second doped region. The floating gate and the first doped region are partially overlapped, and/or the floating gate and the second doped region are not overlapped and a sidewall of the floating gate adjacent to the second doped region and a boundary between the second doped region and the channel region are separated by a distance.”

The patent application was filed on 2021-09-10 (17/471168).