NplusT: TestMesh TMA-100 All-In-One Instrument for Memory Technology Evaluation

NplusT Srl announces TMA- 100, built on the TestMesh platform, dedicated to the evaluation and characterization of new NVM technologies.

Data is everywhere and data needs storage. Emerging NVM technologies like ReRAM, MRAM, PCM, FeRAM and others are being developed for optimized performance in a range of applications from wearable devices to high-performance data centers. The evaluation of such technologies requires complex analog measurements, considering the analog nature of the memory cells and the necessity to obtain a large quantity of accurate data.

NVM, beyond performance and low power consumption, have to ensure a stable operation over their lifetime. During evaluation, the number of write operations (endurance) needs also to be verified. Considering that certain technologies are specified for 10⁹ or in some cases even for 10¹¹ cycles, bringing to end-of-life a test array, without the adequate test environment, might take months or even years.

TestMesh TMA-100 – as a turn-key solution – increases the efficiency of the evaluation, in terms of setup and execution times as well as overall costs.

TestMesh TMA-100 GUI main page
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All-in-one instrument

• Integrates analog and digital signal generations, current sensing, signal capture and switch matrix, embeds even the control computer

• Supplied with a ready-to-use software

• Connected to the company’s array data analysis suite for immediate consultation of the results

Speed-optimized architecture for super-fast cycling

• Current sensing in microseconds

• 1-bit ADC with smart filtering for fast decisions

• Selection of the analog and digital signal waveforms (pulses, addressing, … ) in microseconds

• Programmable sequencer for intelligent algorithm execution via hardware

TestMesh TMA-100 architecture

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Using TMA-100, engineers can focus on their technology bring-up tasks saving effort in the development of the test environment. Information about device characteristics and lifetime is obtained in a shorter time, sometimes by 3-4 orders of magnitude, than with traditional approaches, without the need to design complex support circuits in the device under test.