Powerchip Semiconductor Manufacturing Assigned Three Patents

SRAM and manufacturing
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, Taiwan, has been assigned a patent (11488965) developed by Chang, Shou-Zen,Taichung, Taiwan, Wei, Yi-Hsung,Taoyuan, Taiwan, Tseng, Pei-Hsiu, Tainan, Taiwan, and Lin, Jia-You, Hsinchu, Taiwan, for “SRAM device and manufacturing method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An SRAM memory device includes a substrate, a first transistor, a second transistor, a metal interconnect structure, and a capacitor. The metal interconnect structure is formed on the first and second transistors. The capacitor is disposed in the metal interconnect structure and coupled between the first transistor and the second transistor. The capacitor includes a lower metal layer, a first electrode layer, a dielectric layer, a second electrode layer, and an upper metal layer from bottom to top. The lower metal layer is coupled to a source node of the first transistor and a source node of the second transistor. The lower metal layer and an n-th metal layer in the metal interconnect structure are formed of a same material, wherein n≥1, the upper metal layer and an m-th metal layer in the metal interconnect structure are formed of a same material, wherein m≥n+1.”

The patent application was filed on 2020-07-29 (16/942731).

Semiconductor memory with data protection function and method
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, Taiwan, has been assigned a patent (11475963) developed by Yoshida; Munehiro, Kanagawa, Japan, for “semiconductor memory with data protection function and data protection method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor memory and a data protection method are provided. The semiconductor memory includes a memory array, a switch circuit, a control circuit and a power-down monitor circuit. The switch circuit is coupled to the memory array. The control circuit is coupled to the switch circuit. The power-down monitor circuit is coupled to the control circuit and a supply voltage. The power-down monitor circuit is configured to determine whether that the supply voltage drops below a first power-down detect level during a programming period, to output a trigger signal to the control circuit. The control circuit executes a reset sequence of the semiconductor memory according to the trigger signal. The first power-down detect level is lower than a minimum value of the supply voltage recorded in a datasheet of the semiconductor memory.”

The patent application was filed on 2021-03-19 (17/206141).

Hybrid memory structure
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, Taiwan, has been assigned a patent (11437347) developed by Ma; Chen-Liang, Taoyuan, Taiwan, and Wang; Zih-Song, Nantou County, Taiwan, for a “hybrid memory structure.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A hybrid memory structure including a substrate, a flash memory, a first resistive random access memory (RRAM), and a second RRAM is provided. The flash memory is located on the substrate. The flash memory includes a gate, a first doped region, and a second doped region. The gate is located on the substrate. The first doped region is located in the substrate on one side of the gate. The second doped region is located in the substrate on another side of the gate. The first RRAM is electrically connected to one of the gate, the first doped region, and the second doped region. The second RRAM is electrically connected to another of the gate, the first doped region, and the second doped region.”

The patent application was filed on 2020-09-28 (17/033945).