R&D: Vertical Ferroelectric Thin-Film Transistor Array With 10-nm Gate Length for High-Density 3D Memory Applications

Applied Physics Letters has published an article written by Ik-Jyae Kim, Min-Kyu Kim, and Jang-Sik Lee, Department of Materials Science and Engineering, Pohang University of Science and Technology (POSTECH), Pohang 37673, South Korea.

Abstract: “Hafnia-based ferroelectric thin-film transistors (FeTFTs) are regarded as promising candidates for future nonvolatile memory devices owing to their low power consumption, high operational speed, and complementary metal–oxide–semiconductor compatibility. However, the scalability of hafnia-based materials and the feasibility of three-dimensional (3D) device fabrication should be confirmed for ultrahigh-density memory applications. In this work, we demonstrate that FeTFTs can be scaled down to a 10-nm dimension using the vertical structure with a hafnia-based ferroelectric gate insulating layer and an oxide semiconductor channel. We show that such vertical FeTFTs can be operated with an effective device size of 0.005 μm², a fast operation speed of <100 ns, and a high endurance of 10⁸ cycles. Additionally, the string-level NAND operation is demonstrated using the vertical FeTFT array. Finally, device simulation confirms the possibility of ultrahigh-density 3D ferroelectric NAND with 200 gate stacks. These results demonstrate the ultrahigh scalability of FeTFTs as a promising candidate for next-generation 3D nonvolatile memory.“