Availability of Rambus PCIe 6.0 Interface Subsystem

Summary:

• Delivers data rate of up to 64GT/s for high-performance workloads
• Supports the feature set of PCIe 6.0 with PHY support for CXL 3.0
• Offers complete IP solution optimized for latency, power, and area
• Provides security to protect valuable data assets

Rambus Inc. announced the availability of its PCIe 6.0 interface subsystem comprised of PHY and controller IP.

The company’s PCIe Express 6.0 PHY supports the latest version of the Compute Express Link (CXL) spec, version 3.0.

“The rapid advancement of AI/ML and data-intensive workloads is driving the continued evolution of data center architectures requiring ever higher levels of performance,” said Scott Houghton, GM, interface IP. “The Rambus PCIe 6.0 Interface Subsystem supports the performance requirements of next-generation data centers with premier latency, power, area and security.” 

The company’s PCIe 6.0 interface subsystem delivers data rates of up to 64GT/s and has been optimized to meet the needs of advanced heterogenous computing architectures. Within the subsystem, the PCIe controller features an Integrity and Data Encryption (IDE) engine dedicated to protecting the PCIe links and the valuable data transferred over them. On the PHY side, support for CXL 3.0 is available to enable chip-level solutions for cache-coherent memory sharing, expansion and pooling.

“PCIe is ubiquitous in the data center and CXL will become increasingly important as companies pursue ever-escalating speeds and bandwidths to support higher levels of performance in next-generation applications,” said Shane Rau, research VP, computing semiconductors, IDC. “As a growing number of chip companies emerge to support new data center architectures, access to high-performance interface IP solutions will be key to enabling the ecosystem.”

Key features of company’s PCIe 6.0 Interface Subsystem include:

• Supports PCIe 6.0 spec including 64GT/s data rate and PAM4 signaling 
• Implements low-latency Forward Error Correction (FEC) for link robustness 
• Supports fixed-sized FLITs that enable high-bandwidth efficiency 
• Backward compatible to PCIe 5.0, 4.0 and 3.0/3.1 
• Security with an IDE engine (controller) 
• Supports CXL 3.0 for new use models that optimize memory resources (PHY)

Resources:
Blog: Boosting Data Center Performance to the Next Level with PCIe 6.0 & CXL 3.0
Blog: PCIE 6.0 – All you need to know about PCI Express Gen6