GlobalFoundries Assigned Eight Patents

NVM with metal-insulator-metal (MIM) capacitor in substrate and integration schemes
GlobalFoundries Singapore Ptd. Ltd., Singapore, Singapore , has been assigned a patent (11,456,306) developed by Mun, Bong Woong, and Koo, Jeoung Mo, Singapore, Singapore, for a “nonvolatile memory device with a metal-insulator-metal (MIM) capacitor in a substrate and integration schemes.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A nonvolatile memory device is provided. The nonvolatile memory device comprises a floating gate arranged over a first active region, whereby the first active region is in an active layer of a substrate. A metal-insulator-metal (MIM) capacitor may be provided laterally adjacent to the floating gate, whereby a portion of the metal-insulator-metal capacitor is in the active layer. A contact pillar may connect a first electrode of the metal-insulator-metal capacitor to the floating gate.”

The patent application was filed on November 23, 2020 (17/100,954).

Partially silicided NVM and integration schemes
GlobalFoundries Singapore Ptd. Ltd., Singapore, Singapore , has been assigned a patent (11,450,677) developed by Wang, Lanxiang, Tan, Shyue Seng, Cai, Xinshu, Toh, Eng Huat, and Sun, Yongshun, Singapore, Singapore, for “partially silicided nonvolatile memory devices and integration schemes.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A nonvolatile memory device may be provided. The nonvolatile memory device comprises an active region, an n-well region and an isolation region separating the active region and the n-well region. A floating gate may be provided. The floating gate may be arranged over a portion of the active region and over a first portion of the n-well region. A first doped region in the active region may be laterally displaced from the floating gate on a first side and a second doped region in the active region may be laterally displaced from the floating gate on a second side opposite to the first side. A contact may be arranged over the n-well region, whereby the contact may be laterally displaced from a first corner of the floating gate over the first portion of the n-well region. A silicide exclusion layer may be arranged at least partially over the floating gate.”

The patent application was filed on November 9, 2020 (17/093,602).

Memory devices and methods of forming memory
GlobalFoundries Singapore Ptd. Ltd., Singapore, Singapore , has been assigned a patent (11,444,125) developed by Loy, Desmond Jia Jun, Toh, Eng Huat, and Tan, Shyue Seng, Singapore, Singapore, for “memory devices and methods of forming memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device may be provided, including first, second and third electrodes, first and second mask elements and a switching layer. The first mask element may be arranged over a portion of and laterally offset from the first electrode. The second electrode may be arranged over the first mask element. The second mask element may be arranged over the second electrode. The third electrode may be arranged over a portion of and laterally offset from the second mask element. The switching layer may be arranged between the first electrode and the third electrode, along a first side surface of the first mask element, a first side surface of the second electrode and a first side surface of the second mask element.”

The patent application was filed on June 17, 2020 (16/903,503).

Memory and methods of making
GlobalFoundries Singapore Ptd. Ltd., Singapore, Singapore , has been assigned a patent (11,437,568) developed by Shen, Yanping, Saratoga Springs, NY, Wang, Haiting, and Gu, Sipeng, Clifton Park, NY, for “memory device and methods of making such a memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “One illustrative memory cell disclosed herein includes at least one layer of insulating material having a first opening and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer includes a spacer opening. The memory cell also includes a bottom electrode positioned within the spacer opening, a memory state material positioned above an upper surface of the bottom electrode and above an upper surface of the internal sidewall spacer, and a top electrode positioned above the memory state material.”

The patent application was filed on March 31, 2020 (16/836,434).

Split gate flash memory cells with trench-formed select gate
GlobalFoundries Singapore Ptd. Ltd., Singapore, Singapore , has been assigned a patent (11,404,549) developed by Cai, Xinshu, Tan, Shyue Seng, Toh, Eng Huat, and Quek, Kiok Boone Elgin, Singapore, Singapore, for “split gate flash memory cells with a trench-formed select gate.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Structures for a split gate flash memory cell and methods of forming a structure for a split gate flash memory cell. A trench is formed in a semiconductor substrate. First and second source/drain regions are formed in the semiconductor substrate. A first gate is laterally positioned between the trench and the second source/drain region, and a second gate includes a portion inside the trench. The first source/drain region is located in the semiconductor substrate beneath the trench. A dielectric layer is positioned between the portion of the second gate inside the trench and the semiconductor substrate.”

The patent application was filed on September 21, 2020 (17/026,436).

NVM elements with filament confinement
GlobalFoundries Singapore Ptd. Ltd., Singapore, Singapore , has been assigned a patent (11,393,979) developed by Loy, Desmond Jia Jun, Toh, Eng Huat, Liu, Bin, and Tan, Shyue Seng, Singapore, Singapore, for “non-volatile memory elements with filament confinement.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Structures for a non-volatile memory and methods of forming and using such structures. A resistive memory element includes a first electrode, a second electrode, and a switching layer arranged between the first electrode and the second electrode. A transistor includes a drain coupled with the second electrode. The switching layer has a top surface, and the first electrode is arranged on a first portion of the top surface of the switching layer. A hardmask, which is composed of a dielectric material, is arranged on a second portion of the top surface of the switching layer.”

The patent application was filed on September 30, 2020 (17/038,748).

Vertical memory devices
GlobalFoundries Singapore Ptd. Ltd., Singapore, Singapore , has been assigned a patent (11,367,750) developed by Singh, Sunil Kumar, Mechanicville, NY, Tran, Xuan Anh, Boise, ID, Ramanathan, Eswar, Kalaga, Suryanarayana, Mechanicville, NY, Child, Craig M., Gansevoort, NY, and Fox, Robert, Greenfield Center, NY, for “vertical memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure relates to semiconductor structures and, more particularly, to a vertical memory devices and methods of manufacture. The structure includes: a first bit cell with a first top electrode, a second bit cell with a second top electrode, and a common bottom electrode for both the first bit cell and the second bit cell.”

The patent application was filed on June 12, 2019 (16/439,101).

Resistive random access memory
GlobalFoundries Singapore Ptd. Ltd., Singapore, Singapore , has been assigned a patent (11,335,852) developed by Loy, Desmond Jia Jun, Toh, Eng Huat, and Tan, Shyue Seng, Singapore, Singapore, for “resistive random access memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a dielectric layer having an opening, sidewalls along the opening, a first electrode in the opening, a resistive layer disposed upon the first electrode, an oxygen scavenging layer disposed upon the resistive layer, and a second electrode in contact with the oxygen scavenging layer. The oxygen scavenging layer includes a material that is different from the resistive layer and partially covers the resistive layer. The first electrode is electrically linked to the second electrode by the oxygen scavenging layer and the resistive layer.”

The patent application was filed on September 21, 2020 (17/026,303).