Fadu Assigned Two Patents

Memory controller and storage device including same
Fadu Inc., Seoul, Korea, has been assigned a patent (11,416,168) developed by Kim, Hongseok, Nam, EHyun, Seoul, Korea, Woo, Yeong-Jae, Guri-si, Korea, and Choi, Jin-yong, Seongnam-si, Korea, for “memory controller and storage device including the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory controller and a storage device including the same are provided. The memory controller for performing a buffering operation of temporarily storing data to be written to a non-volatile memory and data to be read from the non-volatile memory in a buffer memory includes a buffer request queue configured to store a plurality of buffer write requests requesting data to be temporarily stored in the buffer memory and a plurality of buffer read requests requesting data stored in the buffer memory to be read, a buffer traffic monitor configured to calculate the total amount of requested data in real time by summing the lengths of data specified in the respective buffer write requests and the respective buffer read requests stored in the buffer request queue, and a buffer manager configured to control execution of the buffering operation by setting an execution ratio based on the total amount of requested data calculated in real time.”

The patent application was filed on November 6, 2020 (17/091,085).

Memory controller and storage device
Fadu Inc., Seoul, Korea, has been assigned a patent (11,385,831) developed by Kim, Eui Jin, Seongnam-si, Korea, Kim, Hongseok, Nam, EHyun, and Sun, Kyoungmoon, Seoul, Korea, for “memory controller and storage device including the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory controller and a storage device including the same are provided. The memory controller includes memory channel controllers configured to perform erase, program, read, erase suspend and program suspend operations for flash memories, a flash translation layer configured to control the memory channel controllers to process write/read commands, allocate a buffer space in a buffer memory in response to a write command in the write/read commands, temporarily store data in the allocated buffer space, and deallocate the buffer spaceaafter the data is programmed to the flash memory, a host interface configured to receive the write/read commands from a host and transmit the received write/read commands to the flash translation layer, and a suspend-limit changer configured to dynamically change an erase/program suspend-limit based on the size of the allocable buffer space, the erase/program suspend-limit being a maximum allowed number of erase/program suspend operations.”

The patent application was filed on August 27, 2020 (17/004,335).