Anaflash Assigned Three Patents

Logic compatible embedded flash memory
Anaflash Inc., San Jose, CA, has been assigned a patent (11,361,802) developed by Song, Seung-Hwan, Palo Alto, CA, for a “logic compatible embedded flash memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory combines a data cell and a reference cell. The data cell includes a coupling structure and a transistor stack. The transistor stack is electrically coupled to the coupling structure. The data cell can store data and output a data signal that corresponds to the data. The reference cell includes a transistor stack that has the same structure as that of the data cell and outputs a reference signal. A column circuit is electrically coupled to the data cell and the first reference cell and configured to process the data signal using the reference signal.”

The patent application was filed on February 11, 2021 (17/173,646).

Neural network circuits having non-volatile synapse arrays
Anaflash Inc., San Jose, CA, has been assigned a patent (11,361,216) developed by Song, Seung-Hwan, Hur, Ji Hye, San Jose, CA, and Lee, Sang-Soo, Cupertino, CA, for a “neural network circuits having non-volatile synapse arrays.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A synapse circuit of a non-volatile neural network. The synapse includes: an input signal line, a reference signal line, an output line, and a cell for generating the output signal. The cell includes: an upper select transistor having a gate that is electrically coupled to the input signal line, and a resistive changing element having one end connected to the upper select transistor in series and another end electrically coupled to the reference signal line. The value of the resistive changing element is programmable to change the magnitude of an output signal. The drain of the upper select transistor is electrically coupled to the first output line.”

The patent application was filed on January 20, 2019 (16/252,640).

Neural network circuits having non-volatile synapse arrays
Anaflash Inc., San Jose, CA, has been assigned a patent (11,361,215) developed by Song, Seung-Hwan, San Jose, CA, and Lee, Sang-Soo, Cupertino, CA, for a “neural network circuits having non-volatile synapse arrays.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile synapse circuit of a non-volatile neural network. The synapse includes: an input signal line, a reference signal line, first and second output lines, and first and second cells for generating the first and second output signals, respectively. Each of the first and second cells includes: an upper select transistor having a gate that is electrically coupled to the input signal line, and a resistive changing element having one end connected to the upper select transistor in series and another end electrically coupled to the reference signal line. The value of the resistive changing element is programmable to change the magnitude of an output signal. The drain of the upper select transistor of the first cell is electrically coupled to the first output line and the drain of the upper select transistor of the second cell is electrically coupled to the second output line.”

The patent application was filed on November 20, 2018 (16/196,617).