eMemory Technology Assigned Eight Patents

Offset cancellation voltage latch sense amplifier for non-volatile memory
eMemory Technology Inc., Hsinchu, Taiwan, has been assigned a patent (11,295,788) developed by Ku, Wei-Ming, Zhubei, Taiwan, for an “offset cancellation voltage latch sense amplifier for non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method provided herein is adapted to a sense amplifier having a first cross-coupled latch and a second cross-coupled latch, each of which includes a first pair of transistors and a pair of coupling capacitors coupled to respective gate terminals of the first pair of transistors. The method includes, during a first phase, charging the pair of coupling capacitors of a first pair of transistors at a first cross-coupled latch to achieve zeroing and providing a first set of input voltages to a second cross-coupled latch, and, during a second phase following the first phase, discharging the pair of coupling capacitors to cancel a mismatch between the first pair of transistors and comparing the first set of input voltages provided to the second cross-coupled latch to generate a first set of output voltages.”

The patent application was filed on June 25, 2020 (16/912,144).

Erasable programmable NVM including two floating gate transistors with same floating gate
eMemory Technology Inc., Hsinchu, Taiwan, has been assigned a patent (11,282,844) developed by Hsu, Chia-Jung, and Sun, Wein-Town, Hsinchu County, Taiwan, for an “erasable programmable non-volatile memory including two floating gate transistors with the same floating gate.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An erasable programmable non-volatile memory includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. A select gate and a first source/drain terminal of the first select transistor receive a first select gate voltage and a first source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the first floating gate transistor are connected with a second source/drain terminal of the first select transistor and a first bit line voltage, respectively. A select gate and a first source/drain terminal of the second select transistor receive a second select gate voltage and a second source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the second floating gate transistor are connected with the second source/drain terminal of the second select transistor and a second bit line voltage, respectively.”

The patent application was filed on February 21, 2019 (16/281,165).

NVM with multi-level cell array and associated read control
eMemory Technology Inc., Hsinchu, Taiwan, has been assigned a patent (11,264,092) developed by Chang, Chia-Fu, Ku, Wei-Ming, and Liao, Hung-Yi, Hsinchu County, Taiwan, for a “non-volatile memory with multi-level cell array and associated read control method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit and a judging circuit. The cell array includes plural multi-level memory cells in an m.times.n array. The cell array is connected with m word lines and n lines. The current supply circuit provides one of plural reference currents according to a current control value. The path selecting circuit is connected with the current supply circuit and the n bit lines. The judging circuit is connected with the path selecting circuit, and generates n output data. A first path selector of the path selecting circuit is connected with a path selecting circuit and a first bit line. A first judging device of the judging circuit is connected with the first path selector and generates a first output data.”

The patent application was filed on August 11, 2020 (16/989,929).

Programming and verifying method for multilevel memory cell array
eMemory Technology Inc., Hsinchu, Taiwan, has been assigned a patent (11,250,921) developed by Chen, Ying-Je, Ku, Wei-Ming, and Sun, Wein-Town, Hsinchu County, Taiwan, for “programming and verifying method for multilevel memory cell array.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A programming and verifying method for a multi-level memory cell array includes following steps. In a step (a1), a first row of the multi-level memory cell array is set as a selected row, and A is set as 1. In a step (a2), memory cells in the selected row excluding the memory cells in the target storage state and bad memory cells are programmed to the A-th storage state. In a step (a3), if A is not equal to X, 1 is added to X and the step (a2) is performed again. In a step (a4), if A is equal to X, the program cycle is ended. In the step (a2), the first-portion memory cells of the selected row are subjected to plural write actions and plural verification actions until all of the first-portion memory cells reach the A-th storage state.”

The patent application was filed on October 14, 2020 (17/069,889).

Memory cell with isolated well region and associated NVM
eMemory Technology Inc., Hsinchu, Taiwan, has been assigned a patent (11,245,004) developed by Chen, Hsueh-Wei, Chen, Wei-Ren, and Sun, Wein-Town, Hsinchu County, Taiwan, for “memory cell with isolated well region and associated non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A non-volatile memory includes a substrate region, a barrier layer, an N-type well region, an isolation structure, a first gate structure, a first sidewall insulator, a first P-type doped region, a second P-type doped region and an N-type doped region. The isolation structure is arranged around the N-type well region and formed over the barrier layer. The N-type well region is surrounded by the isolation structure and the barrier layer. Consequently, the N-type well region is an isolation well region. The first gate structure is formed over a surface of the N-type well region. The first sidewall insulator is arranged around the first gate structure. The first P-type doped region, the second P-type doped region and the N-type doped region are formed under the surface of the N-type well region.”

The patent application was filed on September 30, 2020 (17/037,781).

NVM with multi-level cell array and associated program control
eMemory Technology Inc., Hsinchu, Taiwan, has been assigned a patent (11,170,861) developed by Chang, Chia-Fu, and Liao, Hung-Yi, Hsinchu County, Taiwan, for “non-volatile memory with multi-level cell array and associated program control method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit and a verification circuit. The cell array includes plural multi-level memory cells in an m.times.n array. The cell array is connected with m word lines and n lines. Each of the plural multi-level memory cells is in one of X storage states. The current supply circuit provides plural reference currents. The path selecting circuit is connected with the current supply circuit and the n bit lines. The verification circuit is connected with the path selecting circuit, and generates n verification signals. A first path selector of the path selecting circuit is connected with a path selecting circuit and a first bit line. A first verification device of the verification circuit is connected with the first path selector and generates a first verification signal.”

The patent application was filed on July 27, 2020 (16/939,573).

Multi-time programming non-volatile memory
eMemory Technology Inc., Hsinchu, Taiwan, has been assigned a patent (11,164,880) developed by Lo, Chun-Yuan, Wang, Shih-Chen, Ching, Wen-Hao, Chen, Chih-Hsin, and Chen, Wei-Ren, Hsinchu County, Taiwan, for “multi-time programming non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.”

The patent application was filed on March 29, 2019 (16/369,686).

Determining proper program voltage for plurality of memory cells
eMemory Technology Inc., Hsinchu, Taiwan, has been assigned a patent (11,120,848) developed by Lin, I-Lang, Hsinchu County, Taiwan, for a “method for determining a proper program voltage for a plurality of memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method for operating a plurality of memory cells includes performing a read operation to each of the plurality of memory cells. If at least one memory cell of the plurality of memory cells is determined to be in a programmed state, perform an erasing test operation to the at least one memory cell with an initial erase voltage being applied to the erase line, and perform a verification operation to the at least one memory cell. If the cell current is smaller than the reference current, generate an intermediate erase voltage by adding a step voltage to an erase voltage currently used, and perform the erasing test operation to the at least one memory cell with the intermediate erase voltage being applied to the erase line. Performing the verification operation to the at least one memory cell again.”

The patent application was filed on August 11, 2020 (16/989,901).