STMicroelectronics International Assigned Patent

STMicroelectronics International N.V., Geneva, Switzerland, has been assigned a patent (11,281,795) developed by Kumar, Dhulipalla Phaneendra, Noida, India, for a “hierarchical random scrambling of secure data storage resulting in randomness across chips and on power on resets of individual chips.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A system includes a random number generator generating a random number in response to an event. Control logic generates hierarchical part alignment selectors from the random number. For each secure data block to be stored in volatile storage, a physical address of a first logical address for that secure data block is set based upon the hierarchical part alignment selectors. For each data word within that secure data block, a physical address of a first logical address for that data word is set based upon the hierarchical part alignment selectors. For each data byte within that data word, a physical address of a first logical address for that data byte is set based upon the hierarchical part alignment selectors. A physical address of a logical address for a first data bit within that data byte is set based upon the hierarchical part alignment selectors.”

The patent application was filed on December 24, 2019 (16/726,498).