R&D: Low Temperature Solder (LTS) Paste Characterization for Memory Module and SSD Product Level Reliability Tests

IEEE Xplore has published, in 2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC) proceedings,an article written by C. M. Chen, C. L. Gan, Kal Wilson, Tracy Tennant, Henry Du, Kok Wai Wong, Xue Yong Ang, and Hem Takiar, Micron Technology, Inc No. 369, Sec 4, Sanfeng Rd., Houli Dist., Taichung City, Taiwan.

Abstract: “In order to investigate and characterize LTS (low temperature solder paste) performance, 2 types of LTS pastes were selected for Memory module and SSD which are assembled in different forms for test items. For Dual In-line Memory Module (DIMM), reliability testing include temperature cycling with different cycling conditions, biased HAST, vibration TC, module 3pt bend, module torsion, shock, random vibration, and solder joint Bi% mixing area analysis. For Solid State Drive (SSD), evaluated reliability items include temperature cycling, biased HAST, shock, random vibration, and solder joint Bi% mixing area analysis. For sample batches in this study, Bismuth (Bi) mixing area ratio of Hybrid SAC-LTS solder joint is controlled around 30% to 60%, and has higher joint height compared to SACSAC joints. Reliability-wise, performance of temperature cycling is the main challenge among various reliability test items. The improvement strategy of temperature cycling is the key topic discussed in this paper.“