R&D: Analysis of Residual Stresses Induced in Confined 3D NAND Flash Memory Structure for Process Optimization

IEEE Journal of the Electron Devices Society has published an article written by Eun-Kyeong Jang, Ik-Jyae Kim, Pohang University of Science and Technology, Pohang, South Korea, Cheon An Lee, Chiweon Yoon, Flash Design Team, Samsung Electronics, Company Ltd., Hwasung, South Korea, and Jang-Sik Lee, Pohang University of Science and Technology, Pohang, South Korea.

Abstract: “In flash memory technology, mechanical stress is considered as one of the major factors that can influence the device performance. Furthermore, mechanical stress can have a greater impact on the electrical performance in 3D NAND than in 2D NAND because 3D NAND has a confined structure. Thus, the mechanical stress and its influence on the 3D NAND need to be investigated. In this study, we simulated the 3D NAND flash to quantify how deposition temperatures of components influenced residual stress and electrical characteristics. The stress distribution and electrical characteristics of the channel were shown to depend on the deposition temperatures of the poly-Si channel, charge trap nitride, tunneling oxide, and tungsten word line in technology computer-aided design simulations. Also, the relationship between residual stress and electrical characteristics was investigated and described using the energy band shift due to residual stress. These results have a potential to improve the cell performances and optimize process parameters in 3D NAND flash process technology.“