Crossbar Assigned Six Patents

Resistive random-access memory and architecture with select and control transistors
Crossbar, Inc., Santa Clara, CA, has been assigned a patent (11,227,654) developed by Nazarian, Hagop, San Jose, CA, for “resistive random-access memory and architecture with select and control transistors.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor device includes memory devices respectively comprising a selector transistor in series with a control transistor and a memory cell, wherein the control transistor is connected to the memory cell. Control lines of the semiconductor device extend along a first direction, and a first control line is connected to a first memory device control transistor and a second memory device control transistor. Word lines extend in the first direction, and a first word line is connected to a first memory device selector transistor and a second memory device selector transistor. Bitlines extend in a second direction, with a first bitline connected to a first memory device memory cell and a second bitline is connected to a second memory device memory cell. Source lines extend in the second direction, and a first source line is connected to the first memory device selector transistor and the second memory device selector transistor.”

The patent application was filed on filed: July 30, 2020 (16/943,594).

Computing memory architecture
Crossbar, Inc., Santa Clara, CA, has been assigned a patent (11,222,696) developed by Asnaashari, Mehdi, Danville, CA, Nazarian, Hagop, Sucur, Christophe, San Jose, CA, and Dubois, Sylvain, San Francisco, CA, for a “computing memory architecture.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Provided herein is a computing memory architecture. The non-volatile memory architecture can comprise a resistive random access memory array comprising multiple sets of bitlines and multiple wordlines, a first data interface for receiving data from an external device and for outputting data to the external device, and a second data interface for outputting data to the external device. The non-volatile memory architecture can also comprise programmable processing elements connected to respective sets of the multiple sets of bitlines of the resistive random access memory array, and connected to the data interface. The programmable processing elements are configured to receive stored data from the resistive random access memory array via the respective sets of bitlines or to receive external data from the external device via the data interface, and execute a logical or mathematical algorithm on the external data or the stored data and generate processed data.”

The patent application was filed on filed: June 30, 2020 (16/917,261).

Resistive random access memory matrix multiplication structures and methods
Crossbar, Inc., Santa Clara, CA, has been assigned a patent (11,127,460) developed by Asnaashari, Mehdi, Danville, CA, Nazarian, Hagop, Sucur, Christophe, San Jose, CA, and Dubois, Sylvain, San Francisco, CA, for “resistive random access memory matrix multiplication structures and methods.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Provided herein resistive random access memory matrix multiplication structures and methods. A non-volatile memory logic system can comprise a bit line and at a set of wordlines. Also included can be a set of resistive switching memory cells at respective intersections between the bit line and the set of wordlines. The set of resistive switching memory cells are programmed with a value of an input data bit of a first data matrix and receive respective currents on the set of wordlines. The respective currents comprise respective values of an activation data bit of a second data matrix. A resulting value based on a matrix multiplication corresponds to an output value of the bit line.”

The patent application was filed on filed: September 27, 2018 (16/144,765).

Integrating resistive memory system into multicore CPU die to achieve massive memory parallelism
Crossbar, Inc., Santa Clara, CA, has been assigned a patent (11,126,550) developed by Yeung, Donald, Bethesda, MD, Jacob, Bruce L., Annapolis, MD, Asnaashari, Mehdi, Danville, CA, and Dubois, Sylvain, San Francisco, CA, for “integrating a resistive memory system into a multicore CPU die to achieve massive memory parallelism.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Disclosed is a monolithic integrated circuit (IC) computing device with multiple independent process cores (multicore) and embedded, non-volatile resistive memory serving as system memory. The resistive system memory is fabricated above the substrate, and logic circuits embodying the process cores are fabricated on the substrate. In addition, access circuitry for operating on the resistive system memory, and circuitry embodying memory controllers, routing devices and other logic components is provided at least in part on the substrate. Large main memory capacities of tens or hundreds of gigabytes (GB) are provided and operable with many process cores, all on a single die. This monolithic integration provides close physical proximity between the process cores and main memory, facilitating significant memory parallelism, reduced power consumption, and eliminating off-chip main memory access requests.”

The patent application was filed on filed: September 4, 2018 (16/121,339).

Secure circuit integrated with memory layer
Crossbar, Inc., Santa Clara, CA, has been assigned a patent (11,068,620) developed by Minassian, George, Santa Clara, CA, for a “secure circuit integrated with memory layer.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An example secure circuit device includes a logic layer with a logic circuit, first and second memory layers, and connectors between the logic layer and the memory layers. The logic circuit executes logic operations in response to being in an unlocked state and does not execute logic operations in response to being in a locked state. The logic circuit is in the unlocked state in response to a security key being accessible and in the locked state when the security key is inaccessible. The first memory layer is disposed over a second memory layer with the first and second memory layers being disposed over the logic layer in a monolithic structure. The security key includes a first security key portion disposed in the first memory layer and a second security key portion disposed in the second memory layer.”

The patent application was filed on filed: November 9, 2012 (13/673,951).

Resistive random access memory program and erase techniques and apparatus
Crossbar, Inc., Santa Clara, CA, has been assigned a patent (10,998,064) developed by Guy, Jeremy, San Jose, CA, Jo, Sung Hyun, Sunnyvale, CA, Nazarian, Hagop, Shah, Ruchirkumar, San Jose, CA, and Zhao, Liang, Santa Clara, CA, for “resistive random access memory program and erase techniques and apparatus.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for erasing a memory cell includes applying a first erase to memory cells to erase the memory cells, wherein first memory cells are in a weakly erased state in response to the first erase, and wherein second memory cells are in a normally erased state in response to the first erase, thereafter applying a first weak program to the memory cells, wherein the second memory cells enter a programmed state and the third memory cells remain in the erased state in response to the first weak program, and thereafter applying a read to the memory cells to identify the second memory cells, and applying a second erase to the second memory cells to thereby erase the second memory cell.”

The patent application was filed on filed: March 4, 2019 (16/291,467).