GSI Technology Assigned Four Patents

Storage array circuits and methods for computational memory cells
GSI Technology, Inc., Sunnyvale, CA, has been assigned a patent (11,227,653) developed by Shu, Lee-Lean, Soon-Kyu, Park, and Chiang, Paul M., Sunnyvale, CA, for “storage array circuits and methods for computational memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage array for computational memory cells formed as a memory/processing array provides storage of the data without using the more complicated computational memory cells for storage. The storage array may have multiple columns of the storage cells coupled to a column of the computational memory cells. The storage array may have ECC circuitry.”

The patent application was filed on filed: June 4, 2018 (15/997,250).

Read data processing circuits and methods associated with computational memory cells
GSI Technology, Inc., Sunnyvale, CA, has been assigned a patent (11,205,476) developed by Haig, Bob, Ehrman, Eli, Chang, Chao-Hung, and Huang, Mu-Hsiang, Sunnyvale, CA, for “read data processing circuits and methods associated with computational memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells connected to the same read bit line.”

The patent application was filed on filed: May 28, 2020 (16/886,537).

Processing array device that performs one cycle full adder operation and bit line read/write logic features
GSI Technology, Inc., Sunnyvale, CA, has been assigned a patent (11,194,548) developed by Shu, Lee-Lean, Haig, Bob, and Chang, Chao-Hung, Sunnyvale, CA, for a “processing array device that performs one cycle full adder operation and bit line read/write logic features.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.”

The patent application was filed on filed: October 6, 2020 (17/064,395).

Results processing circuits and methods associated with computational memory cells
GSI Technology, Inc., Sunnyvale, CA, has been assigned a patent (11,194,519) developed by Haig, Bob, Ehrman, Eli, Ilan, Dan, Chuang, Patrick, Chang, Chao-Hung, and Huang, Mu-Hsiang, Sunnyvale, CA, for “results processing circuits and methods associated with computational memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.”

The patent application was filed on filed: December 13, 2019 (16/713,383).