Marvell Asia Assigned Twenty-One Patents

Transferring data between SSDs via connection between SSDs
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (11,200,193) developed by Haimzon, Avi, Nes Ziona, Israel, Kardashov, Timor, Kyriat Ono, Israel, and Mizrahi, Noam, Modi’in, Israel, for “transferring data between solid state drives (SSDs) via a connection between the SSDs .“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A first solid state drive (SSD) includes a first built-in network interface device configured to communicate via a network fabric, and a second SSD includes a second built-in network interface device configured to communicate via the network fabric. A connection is opened between the first SSD and the second SSD over the network fabric. Based on a non-volatile memory over fabric (NVMe-oF) communication protocol, an NVMe command to transfer data between the first SSD and the second SSD over the connection is encapsulated in a capsule. The capsule is sent from the first SSD to the second SSD over the connection via the network fabric. The second SSD executes the NVMe command in the capsule to transfer the data between the first SSD and the second SSD over the connection.”

The patent application was filed on March 16, 2020 (16/820,308).

Accelerating access to memory banks in storage
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (11,194,733) developed by Haimzon, Avi, Nes Ziona, Israel, and Katz, Adi, Ramat Gan, Israel, for “accelerating access to memory banks in a data storage system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A first master receives a first virtual address in a virtual memory, the first virtual address in the virtual memory corresponding, according to a mapping function, to a first physical address of a first physical memory bank which is to be accessed by the first master. The first master accesses the first physical address to perform a first memory operation in the first memory bank. A second master receives a second virtual address in a virtual memory, the second virtual address in the virtual memory corresponding, according to the mapping function, to a second physical address of a second physical memory bank which is to be accessed by the second master. Concurrently with access by the first master to the first physical address, the second master accesses the second physical address to perform a second memory operation in the second physical memory bank.”

The patent application was filed on February 25, 2020 (16/800,913).

Decoding of high-density memory cells in SSD
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (11,182,288) developed by Ram, B Hari, Chennai, India, Ahirwar, Vijay, Pune, India, Rottela, Sri Varsha, Visakhapatnam, India, and Khude, Nilesh N., Pune, India, for “decoding of high-density memory cells in a solid-state drive.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of decoding data from high density memory includes reading voltage levels from a first memory cell and a set of one or more neighboring memory cells of flash memory in response to a read command with an address corresponding to the first memory cell, inputting the voltage levels into a trained model that has been trained on the flash memory to estimate bit values written to a memory cell based on respective voltage values read from the first memory cell and from the neighboring memory cells according to a layout of memory cells of the flash memory, obtaining from the trained model an estimated bit value written to the first memory cell based on the respective voltage levels of the first memory cell and the neighboring memory cells having been input into the trained model, and outputting the estimated hit value in response to the read command.”

The patent application was filed on February 20, 2020 (16/796,378).

Adaptation of two-dimensional magnetic recording channel
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (11,145,331) developed by Nangare, Nitin, Sunnyvale, CA, and Shen, Jinlu, Pullman, WA, for “systems and methods for adaptation of a two-dimensional magnetic recording channel.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems and methods for adaptation of a two-dimensional magnetic recording (TDMR) channel are provided. Read-back signals from respective read sensors of a TDMR channel are received at an equalizer, the read-back signals corresponding to a digital signal value. A log-likelihood ratio (LLR) signal is generated based at least in part on the read-back signals. A cross-entropy value is generated indicative of a mismatch between a probability of detected bit and a probability of the true recorded bit. The equalizer is adapted by setting an equalizer parameter to a value that corresponds to a minimum cross-entropy value from among the computed cross-entropy value and one or more previously computed cross-entropy values, to decrease a read-back bit error rate for the TDMR channel.”

The patent application was filed on October 29, 2020 (17/084,370).

Mobile storage for storing and transferring data generated by IoT devices
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (11,134,135) developed by Chang, Runzi, Saratoga, CA, for “mobile storage system for storing and transferring data generated by Internet of Things (IoT) devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A mobile storage system receives, by a short range network interface, data from an internet of things (IoT) device. The data is stored in storage. A communication bandwidth to a cloud data storage and a power level of a power supply is determined. Based on the communication bandwidth to the cloud data storage and the power level of the power supply, the data to the cloud data storage is transferred via a long range network interface.”

The patent application was filed on September 18, 2019 (16/574,229).

High-density high-bandwidth (SRAM) with phase shifted sequential read
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (11,114,155) developed by Arsovski, Igor, Williston, VT, Patil, Akhilesh, South Burlington, VT, and Hunt-Schroeder, Eric D., Essex Junction, VT, for a “high-density high-bandwidth static random access memory (SRAM) with phase shifted sequential read.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure relates to a structure including a read controller configured to receive a burst enable signal and a word line pulse signal, identify consecutive read operations from storage cells accessed via a word line, precharge bit lines once during consecutive, sequential reads, and hold the word line active through N-1 of the consecutive read operations, and N is an integer number of the consecutive read operations.”

The patent application was filed on January 24, 2019 (16/256,584).

Dual-use semiconductor device for solar power and storage
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (11,101,389) developed by Ahirwar, Vijay, Pune, India, Rottela, Sri Varsha, Visakhapatnam, India, Khude, Nilesh N, Pune, India, and Ram, B Hari, Chennai, India, for “dual-use semiconductor device for solar power and data storage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure describes aspects of a dual-use semiconductor device for solar power and data storage. In some aspects, a dual-use semiconductor device is selectively configured to generate power by coupling regions having a same type of doping to form a PN junction by which power is generated in response to light. The generated power may be provided to a load coupled to contacts (e.g., front and backside contacts) of the dual-use semiconductor device. The dual-use semiconductor device is also selectively configurable for data storage by decoupling the regions of the same type of doping to provide respective data storage access terminals for accessing (e.g., writing or reading) a bit value that is stored as a level of charge by a floating-gate structure of the dual-use semiconductor device. By so doing, solar power arrays implemented with dual-use semiconductor devices may also provide data storage functionality.”

The patent application was filed on February 20, 2020 (16/796,680).

Providing quality of service over virtual interface for solid-state storage
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (11,074,013) developed by Suri, Salil, Fremont, CA, Kishore, Ramaswami, San Francisco, CA, and Gonar, Kalyan Prabhu, Mountain View, CA, for “apparatus and methods for providing quality of service over a virtual interface for solid-state storage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure describes aspects for providing Quality of Service (QoS) over a virtual interface for solid-state storage. In some aspects, a storage media switch receives, from a host device, an input/output (I/O) command for data access including an identifier for a virtual interface associated with a namespace through which solid-state storage is accessible. The switch determines an amount of the data that the I/O command will access through the namespace. A determination is made whether the amount of data that the I/O command will access through the namespace exceeds a predefined threshold for data access through that namespace. In response to determining that the amount of data does not exceed the predefined threshold, the I/O command is released to the solid-state storage to enable the data access. By so doing, the switch may provide QoS for the virtually accessed solid-state storage based on an access parameter of the namespace.”

The patent application was filed on August 6, 2019 (16/533,399).

Generating metadata describing unstructured data objects at storage edge
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (11,068,544) developed by Kudryavtsev, Konstantin, Sunnyvale, CA, Mizrahi, Noam, Modi’in, Israel, Oberg, Mats, Varnica, Nedeljko, San Jose, CA, Nangare, Nitin, Sunnyvale, CA, Polivanyi, Igor, Palo Alto, CA, Ratnayake, Ruwan, San Jose, CA, Jiang, Leo, Fremont, CA, Chau, Quynh, Campbell, CA, and Chang, Wen Lung, Fremont, CA, for “systems and methods for generating metadata describing unstructured data objects at the storage edge.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage control device coupled to a storage device and located remotely from a host device receives media object data from the host device. The storage control device identifies a type of the media object data and select, based on the identified type, a computational model from among a plurality of computational models for use by a computational engine of the storage control device. The computational engine uses the selected computational model to generate metadata describing the media object data. The metadata is stored in the storage device so as to be selectively retrievable from the storage device separately from the media object data.”

The patent application was filed on January 31, 2019 (16/263,387).

Dual-interface flash memory controller with execute-in-place cache control
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (11,061,670) developed by Yang, Ying, Shanghai, China, Yeung, Ken, Cupertino, CA, Xu, Nelson, and Huang, Tung-hao, San Jose, CA, for a “dual-interface flash memory controller with execute-in-place cache control.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A Flash memory controller for a system having first and second microcontrollers configured to perform first and second functions, and further having a Flash memory medium shared by the two microcontrollers, includes first and second execute-in-place cache controllers respectively configured to cache program code retrieved from the Flash memory for execution by the respective microcontrollers. A cache-miss arbiter controls access by the microcontrollers to the Flash memory on occurrence of a cache miss in one of the cache controllers. The arbiter may allow aborting of a first fetching operation on behalf of one of the microcontrollers upon receipt of a fetch request from the other microcontroller if the first fetching operation has retrieved a desired data unit and a threshold amount of data. The Flash memory controller may also include a decryption engine configured to decrypt encrypted program code. The decryption mode is determined from address ranges.”

The patent application was filed on March 4, 2020 (15/929,237).

High density fractional bit SSD using coded set partitions
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (11,061,617) developed by Ahirwar, Vijay, Pune, India, Ram, B Hari, Chennai, India, Rottela, Sri Varsha, Visakhapatnam, India, and Khude, Nilesh N, Pune, India, for a “high density fractional bit solid state drives using coded set partitions.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Fractional bit storage is disclosed herein which allows for storage of additional bits distributed over multiple SSD cells and maximizes data stored for SSD cells with non-binary amounts of allowable threshold voltages while minimizing required bits dedicated to error correction code (ECC). For an SSD cell with twenty-four levels of threshold voltage, set partitioning is used to create three equal subsets of levels each corresponding to eight levels of threshold voltage and each partitioned subset able to encode three bits. Each partitioned subset is designed with eight allowable threshold voltage ranges, each of which is separated from any other allowable threshold voltage range by at least two of the twenty-four levels of maximum threshold voltage. By choosing both set partitioning and assigning bit values determined via code modulation, bits stored within a partitioned subset are protected without the need for additional ECC.”

The patent application was filed on February 20, 2020 (16/796,296).

Codeword interleaving for magnetic storage media
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (11,061,582) developed by Oberg, Mats, San Jose, CA, for a “codeword interleaving for magnetic storage media.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure describes aspects of codeword interleaving for magnetic storage media. In some aspects, segments of a codeword are spread or interleaved across multiple sectors of magnetic storage media. Data for one or more codewords may be received by a read channel and, for each codeword, a respective indicator is selected or received. The indicator may indicate which partitions of the multiple sectors that segments of one of the codewords are to be written. The data is then encoded to provide the codewords and segments of the codewords are placed in an interleaver based on the respective indicator corresponding to the codeword. The codeword segments are written from the interleaver to partitions of the multiple sectors of the magnetic storage media. By so doing, codewords may be spread across multiple sectors, such that a loss of a few sectors does not prevent readback and decoding of the codewords.”

The patent application was filed on February 26, 2020 (16/801,506).

Simultaneous bidirectional serial lanes over USB-C interface
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (11,055,244) developed by Langner, Paul, Fremont, CA, and Edelhaus, Simon, San Ramon, CA, for “apparatus and method for simultaneous bidirectional serial lanes over USB-C interface.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An input/output (I/O) interface system for computing devices is disclosed. The I/O interface system includes an externally-engageable USB-C interface connector. A first I/O protocol controller circuit couples to the USB-C interface connector via multiple bidirectional serial lanes. Each of the bidirectional serial lanes transfers a single serial stream of data in a simultaneously bidirectional manner. A second I/O protocol controller circuit couples to the USB-C interface connector via multiple unidirectional serial lanes. Each of the unidirectional serial lanes transfers a single serial stream of data in a unidirectional manner. Mode control circuitry selects between the first I/O protocol controller circuit and the second I/O protocol controller circuit for data transfers with the USB-C interface connector based on a detected signaling media externally connected to the USB-C interface connector.”

The patent application was filed on May 22, 2019 (16/419,585).

Multiple sense amplifier and data path-based pseudo dual port SRAM
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (11,024,347) developed by Bringivijayaraghavan, Venkatraghavan, Cheyyar, India, Sankar, Arjun, Horamavu Post, India, Chidambaran, Sreejith, Kerala, India, and Arsovski, Igor, Williston, VT, for “multiple sense amplifier and data path-based pseudo dual port SRAM.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device includes a memory array of memory cells, wordlines and bitlines connected to the memory cells, a first read multiplexor and a second read multiplexor connected to the bitlines, a first sense amplifier connected to the first read multiplexor, a second sense amplifier connected to the second read multiplexor, a first data path connected to the first sense amplifier, and a second data path connected to the second sense amplifier. Each of the memory cells is connected to only one pair of the bitlines and only one of the wordlines. The first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle and the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of a clock cycle that is different from the first portion of the clock cycle.”

The patent application was filed on October 17, 2019 (16/655,283).

Securing and controlling remote access of memory-mapped device utilizing ethernet interface and test port of network device
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (11,012,333) developed by Kniplitsch, Thomas, Insheim, Germany, for “securing and controlling remote access of a memory-mapped device utilizing an ethernet interface and test port of a network device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A network device including access and test ports, an interface, and first and second controllers. The interface receives an Ethernet frame transmitted over an Ethernet network to the network device. The Ethernet frame includes bits for testing or debugging the memory-mapped device and is received at the interface based on an output of a host device. The first controller converts the Ethernet frame to a first access frame. The test port receives a diagnostic signal transmitted from the host device to the network device. The second controller converts the diagnostic signal to a second access frame and controls passage of the access frames to the memory-mapped device via the access port. The first controller tests or debugs the memory-mapped device based on data received from a register of the memory-mapped device. The data is written in the register based on the first and second access frames.”

The patent application was filed on January 28, 2020 (16/774,771).

Artificial intelligence-enabled management of storage media access
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (11,010,314) developed by Therene, Christophe, Livermore, CA, Varnica, Nedeljko, San Jose, CA, and Nguyen, Phong Sy, Livermore, CA, for an “artificial intelligence-enabled management of storage media access.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure describes apparatuses and methods for artificial intelligence-enabled management of storage media. In some aspects, a media access manager of a storage media system receives, from a host system, host input/output commands (I/Os) for access to storage media of the storage media system. The media access manager provides information describing the host I/Os to an artificial intelligence engine and receives, from the artificial intelligence engine, a prediction of host system behavior with respect to subsequent access of the storage media. The media access manager then schedules, based on the prediction of host system behavior, the host I/Os for access to the storage media of the storage system. By so doing, the host I/Os may be scheduled to optimize host system access of the storage media, such as to avoid conflict with internal I/Os of the storage system or preempt various thresholds based on upcoming idle time.”

The patent application was filed on October 25, 2019 (16/664,528).

Interleaver for distributed sector storage
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (10,998,001) developed by Varnica, Nedeljko, and Oberg, Mats, San Jose, CA, for an “interleaver for distributed sector storage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for storing data in groups of logical data sectors across a plurality of contiguous data tracks of a data storage medium includes defining a plurality of interleaver patterns, each interleaver pattern including a sector interleaving pattern specifying a respective order in which segments of respective ones of the logical data sectors are spread across physical data sectors of a respective one of the contiguous data tracks. For each respective group of logical data sectors, a respective interleaver pattern is selected. Data is written from each group of logical data sectors to one of the data tracks using the selected interleaver pattern. Each respective group of logical data sectors is written to its respective data track using a different interleaver pattern from any other group of logical data sectors written to an adjacent data track, so that no two adjacent data tracks are written using the same interleaver pattern.”

The patent application was filed on October 5, 2020 (16/948,877).

Pulse-based writing for magnetic storage media
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (10,984,822) developed by Oberg, Mats, San Jose, CA, and Fang, Hao, Eden Prarie, MN, for a “pulse-based writing for magnetic storage media.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure describes aspects of pulse-based writing for magnetic storage media. In some aspects, a pulse-based writer of magnetic storage media determines that a string of data bits having a same polarity corresponds to a magnet longer than a threshold associated with a magnetic media writer. The pulse-based writer inserts, into the string of data bits, a transition to a polarity opposite to the same polarity of the string of data bits. The string of data bits including the inserted transition is then transmitted to the magnetic media writer to cause a write head of the writer to pulse while writing the magnet to magnetic storage media. Various aspects may also implement a control signal to mask a transition or control polarity of the magnetic media writer. By so doing, magnets may be written to the magnetic storage media more efficiently or with less distortion to neighboring tracks.”

The patent application was filed on July 14, 2020 (16/928,971).

Multi-port high performance memory
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (10,978,143) developed by Braceras, George M., Essex Junction, VT, Hu, Xiaoli, Zhao, Wei, Shanghai, China, Arsovski, Igor, Williston, VT, Jin, Yuzheng, Pu, Hao, Zhao, Shuangdi, and Li, Qing, Shanghai, China, for a “multi-port high performance memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A structure includes a multi-port memory including a multiple transistor bitcell single ended read port and a write port, a read circuit which is connected to a multiple transistor bitcell circuit and is also configured to evaluate the multiple transistor bitcell single ended read port, and a timer circuit for the single ended read port and which is configured to generate two successive read pulses in one clock cycle for the multi-port memory.”

The patent application was filed on August 26, 2019 (16/550,953).

Modifying NVMe physical region page list pointers and data pointers to facilitate routing of PCIe memory requests
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (10,977,199) developed by Suri, Salil, Fremont, CA, Li, Yingdong, Palo Alto, CA, and Ho, Szu-Hsien, Fremont, CA, for “modifying NVMe physical region page list pointers and data pointers to facilitate routing of PCIe memory requests.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A first command is received from a virtual or physical host associated with a storage system which includes two or more hosts. The first command comprises one or more physical request page (PRP) entries associated with the non-volatile memory express (NVMe) standard. The one or more PRP entries are modified with an indication of the virtual or physical host. A second command is sent with the modified one or more PRP entries to a solid state drive (SSD). A memory request is received from the SSD, where the memory request comprises the modified one or more PRP entries. The memory request is routed to the virtual or physical host based on the indication of the virtual or physical host in the modified one or more PRP entries.”

The patent application was filed on August 5, 2019 (16/532,186).

Constant-density writing for magnetic storage media
Marvell Asia Pte, Ltd., Singapore, Singapore, has been assigned a patent (10,971,187) developed by Katchmart, Supaket, San Jose, CA, for a “constant-density writing for magnetic storage media.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure describes aspects of constant-density writing for magnetic storage media. In some aspects, a constant-density writer delays transitions between bits within write data to enable constant-density writing. The write data has an initial bit period based on a constant clock signal, which is generated based on the rotation of a media disk. The constant-density writer modifies the write data to generate phase-delayed write data, which has a bit period that is greater than or equal to the initial bit period. To realize this bit period, the constant-density writer changes write phases of bit transitions within the write data. The constant-density writer can also insert stretch bits, filter single-bit transitions, and mitigate glitches within the phase-delayed write data.”

The patent application was filed on March 9, 2020 (16/812,960).