Yangtze Memory Technologies Assigned Twenty Patents

Three-dimensional memory
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,158,622) developed by Zhang, Kun, Wuhan, China, for “three-dimensional memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a P-type doped semiconductor layer above the memory stack, an N-well in the P-type doped semiconductor layer, a plurality of channel structures each extending vertically through the memory stack into the P-type doped semiconductor layer, a conductive layer in contact with upper ends of the plurality of channel structures, at least part of which is on the P-type doped semiconductor layer, a first source contact above the memory stack and in contact with the P-type doped semiconductor layer, and a second source contact above the memory stack and in contact with the N-well.”

The patent application was filed on September 14, 2020 (17/020,416).

Unified semiconductor devices having processor and heterogeneous memories
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,158,604) developed by Cheng, Weihua, and Liu, Jun, Wuhan, China, for “unified semiconductor devices having processor and heterogeneous memories and methods for forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes NAND memory cells and a first bonding layer including first bonding contacts. The semiconductor device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The semiconductor device also includes a third semiconductor structure including a processor, SRAM cells, and a third bonding layer including third bonding contacts. The semiconductor device further includes a first bonding interface between the first and third bonding layers, and a second bonding interface between the second and third bonding layers. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface. The first and second bonding interfaces are in a same plane.”

The patent application was filed on October 30, 2019 (16/669,450).

Operation method for 3D NAND flash and 3D NAND flash
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,158,383) developed by Huang, Kai Jin, Lyu, Jin, and Liu, Gang, Wuhan, China, for “operation method for 3D NAND flash and 3D NAND flash.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An operation method for a 3D NAND flash having a plurality of bit lines, wherein the plurality of bit lines comprises a plurality of layers, the operation method includes defining a plurality of upper layers of the plurality of bit lines of the 3D NAND flash as a plurality of upper select gates and a top layer of the plurality of bit lines of the 3D NAND flash as a top dummy layer, and applying a first voltage on a first top dummy layer of a select bit line of the plurality of bit lines to turn on the first top dummy layer of the select bit line of the plurality of bit lines when programming.”

The patent application was filed on May 11, 2020 (16/872,268).

Memory and erasing and verification
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,158,380) developed by Li, Kaiwei, Jia, Jianquan, Liu, Hongtao, and Zhang, An, Wuhan, China, for “memory device and erasing and verification method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device includes a plurality of memory blocks, and a control circuit. A selected memory block of the plurality of memory blocks comprises a top select gate, a bottom select gate, a plurality of word lines, a common-source line, and a P-well. The control circuit performs an erasing and verification method, wherein the erasing and verification method includes erasing the selected memory block during an erasing stage, and maintaining the bottom select gate to be turned on during a maintaining period before the top select gate are turned on during a verification stage.”

The patent application was filed on June 18, 2020 (16/905,880).

Three-dimensional memory devices having hydrogen blocking layer
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,152,277) developed by Liu, Jun, Wuhan, China, for “three-dimensional memory devices having hydrogen blocking layer and fabrication methods thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of three-dimensional (3D) memory devices have a hydrogen blocking layer and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, an array of NAND memory strings each extending vertically through the memory stack, a plurality of logic process-compatible devices above the array of NAND memory strings, a semiconductor layer above and in contact with the logic process-compatible devices, a pad-out interconnect layer above the semiconductor layer, and a hydrogen blocking layer vertically between the semiconductor layer and the pad-out interconnect layer and configured to block outgassing of hydrogen.”

The patent application was filed on December 26, 2019 (16/727,870).

3D NAND memory
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,145,667) developed by Zhang, Ruo Fang, Wang, Enbo, Yang, Haohao, Xu, Qianbing, Hu, Yushi, and Zhang, Fushan, Wuhan, China, for “3D NAND memory device and method of forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In a memory device, a lower memory cell string is formed over a substrate to include a first channel structure, a plurality of first word line layers and first insulating layers. The first channel structure protrudes from the substrate and passes through the first word line layers and first insulating layers. An inter deck contact is formed over the lower memory cell string and connected with the first channel structure. An upper memory cell string is formed over the inter deck contact. The upper memory cell string includes a second channel structure, a plurality of second word lines and second insulating layers. The second channel structure passes through the second word lines and second insulating layers, and extends to the inter deck contact, and further extends laterally into the second insulating layers. A channel dielectric region of the second channel structure is above the inter deck contact.”

The patent application was filed on March 28, 2019 (16/367,299).

Staircase structure for memory
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,145,666) developed by Lu, Zhenyu, Chen, Jun, Dai, Xiaowang, Zhu, Jifeng, Tao, Qian, Huang, Yu Ru, Hu, Si Ping, Yao, Lan, Xiao, Li Hong, Zheng, A Man, Bao, Kun, and Yang, Haohao, Hubei, China, for a “staircase structure for memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.”

The patent application was filed on May 28, 2020 (16/885,858).

Multi-stack three-dimensional memory
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,145,645) developed by Xiao, Li Hong, and Hu, Bin, Wuhan, China, for “multi-stack three-dimensional memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of three-dimensional (3D) memory devices having multiple memory stacks and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a first device chip, a second device chip, and a bonding interface. The first device chip includes a peripheral device and a first interconnect layer. The second device chip includes a substrate, two memory stacks disposed on opposite sides of the substrate, two memory strings each extending vertically through one of the two memory stacks, and a second interconnect layer. The bonding interface is formed vertically between the first interconnect layer of the first device chip and the second interconnect layer of the second device chip.”

The patent application was filed on February 5, 2020 (16/783,152).

Programming memory system
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,145,362) developed by Liang, Ke, Hou, Chun Yuan, and Tang, Qiang, Wuhan, China, for a “method for programming memory system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for programming a memory system including a plurality of memory cells includes performing a first program operation on the plurality of the memory cells. The method also includes identifying a first memory cell and a second set of memory cell from the plurality of memory cells based on threshold voltages of the plurality of memory cells after performing the first program operations. The method further includes performing a second operation on the plurality of the memory cells by applying a first cross voltage to the first memory cell and a second cross voltage to the second memory cell.”

The patent application was filed on January 27, 2021 (17/160,338).

Memory and programming
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,139,029) developed by Li, Haibo, and Zhang, Chao, Wuhan, China, for “memory device and programming method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A programming method for a memory device includes simultaneously starting to program a first plane and a second plane, and bypassing the first plane and keeping programming the second plane when the first plane has been programmed successfully and the second plane has not been programmed successfully yet.”

The patent application was filed on July 8, 2020 (16/923,100).

Forming three-dimensional phase-change memory
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,133,465) developed by Liu, Jun, Wuhan, China, for “methods for forming three-dimensional phase-change memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A lower bit line contact and a lower bit line in contact with the lower bit line contact are formed. Lower memory cells are formed above and in contact with the lower bit line. Each lower memory cell includes stacked a phase-change memory (PCM) element, a selector, and electrodes. Parallel word lines in a same plane are formed above and in contact with the lower memory cells. Each word line is perpendicular to the lower bit line. Upper memory cells are formed above and in contact with the word lines. Each upper memory cell includes stacked a PCM element, a selector, and electrodes. An upper bit line is formed above and in contact with the upper memory cells. The upper bit line is perpendicular to each word line. An upper bit line contact is formed above and in contact with the upper bit line. At least one of the lower bit line contact and the upper bit line contact is disposed inclusively between the lower and upper memory cells in a plan view.”

The patent application was filed on December 26, 2019 (16/727,853).

Memory cell structure of 3D memory
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,133,325) developed by Dai, Xiaowang, Wuhan, China, Lu, Zhenyu, Hubei, China, Chen, Jun, Wuhan, China, Tao, Qian, Hu, Yushi, Zhu, Jifeng, Dong, Jin Wen, Xia, Ji, Zhang, Zhong, and Li, Yan Ni, Hubei, China, for a “memory cell structure of a three-dimensional memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Various embodiments disclose a 3D memory device, including a substrate, a plurality of conductor layers disposed on the substrate, a plurality of NAND strings disposed on the substrate, and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.”

The patent application was filed on September 22, 2020 (17/028,154).

Vertical memory
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,133,324) developed by Zhang, Zhong, Wuhan, China, for “vertical memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Aspects of the disclosure provide a semiconductor device. The semiconductor device includes gate layers and insulating layers that are stacked alternatingly along a direction perpendicular to a substrate of the semiconductor device in an array region upon the substrate. Further, the semiconductor device includes an array of channel structures that is formed in the array region. The gate layers and the insulating layers are stacked in a staircase form with stair steps having non-uniform stair depths in a connection region upon the substrate. Further, the semiconductor device includes contact structures to the gate layers. The contact structures are formed on the stair steps that have the non-uniform stair depths.”

The patent application was filed on November 15, 2019 (16/684,830).

3D memory with three-dimensional phase-change memory
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,133,293) developed by Liu, Jun, Wuhan, China, for a “three-dimensional memory device with three-dimensional phase-change memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including a substrate, an array of NAND memory cells above the substrate, and a first bonding layer above the array of NAND memory cells. The first bonding layer includes first bonding contacts. The 3D memory device also further includes a second semiconductor structure including a second bonding layer above the first bonding layer and including second bonding contacts, a peripheral circuit and an array of PCM cells above the second bonding layer, and a semiconductor layer above and in contact with the peripheral circuit. The 3D memory device further includes a bonding interface between the first and second bonding layers. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.”

The patent application was filed on January 4, 2021 (17/141,022).

Programming multi-plane memory for accelerating program speed and reducing program disturbance
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,133,077) developed by Deng, Jialiang, and Wang, Yu, Wuhan, China, for “method of programming multi-plane memory device for accelerating program speed and reducing program disturbance.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device includes a plurality of planes, a row driver and a controller. A method of programming the memory device includes in a program operation, the row driver applying a program pulse to a plurality of memory cells of a first plane of the plurality of planes, after the row driver applies the program pulse to the plurality of memory cells, the controller verifying if the plurality of memory cells have reached a predetermined program state, and if a preset number of the plurality of memory cells have failed to reach the predetermined program state after the plurality of memory cells have been verified for a predetermined number of times, the controller disabling the first plane.”

The patent application was filed on April 23, 2020 (16/857,124).

Multi-die peak power management for 3D memory
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,133,038) developed by Tang, Qiang, Hubei, China, for a “multi-die peak power management for three-dimensional memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of a peak power management (PPM) circuit on a memory die are disclosed. The PPM circuit includes a first transistor and a second transistor arranged in parallel, wherein the first and second transistors each has a drain terminal electrically connected to a first power source and a second power source, respectively. The PPM circuit also includes a resistor having a first terminal electrically connected to respective source terminals of the first and second transistors. The PPM circuit further includes a first contact pad on the memory die, electrically connected to a second contact pad on a different memory die through a die-to-die connection. The PPM circuit also includes a third transistor with a drain terminal electrically connected to a second terminal of the resistor, and a source terminal electrically connected to the first contact pad.”

The patent application was filed on September 8, 2020 (17/014,451).

3D memory and forming
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,127,758) developed by Zhu, Hongbin, Wuhan, China, for “three-dimensional memory devices and methods for forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a plurality of memory decks stacked above the substrate. Each of the memory decks includes a gate electrode, a blocking layer on the gate electrode, a plurality of charge trapping layers on the blocking layer, a tunneling layer on the plurality of charge trapping layers, a channel layer on the tunneling layer, and an inter-deck dielectric layer on the channel layer. The plurality of charge trapping layers are discrete and disposed at different levels. A top surface of the inter-deck dielectric layer is nominally flat. The gate electrode of another one of the memory decks immediately above the memory deck is disposed on the top surface of the inter-deck dielectric layer.”

The patent application was filed on December 26, 2019 (16/727,880).

3D memory device with source structure
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,127,757) developed by Xu, Wenxiang, Xu, Wei, Huang, Pan, Yan, Ping, Huo, Zongliang, Zhou, Wenbin, and Xia, Ji, Wuhan, China, for “three-dimensional memory device with source structure and methods for forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack, a plurality of channel structures, and a source structure. The memory stack is over a substrate and includes interleaved a plurality of conductor layers and a plurality of insulating layers. The plurality of channel structures extend vertically in the memory stack. The source structure extend in the memory stack. The source structure includes a plurality of source contacts each in a respective insulating structure, and two adjacent ones of the plurality of source contacts are conductively connected to one another.”

The patent application was filed on October 16, 2019 (16/655,167).

3D memory and forming same
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,127,755) developed by Zhu, Hongbin, Wuhan, China, for “three-dimensional memory devices and methods for forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a gate electrode above the substrate, a blocking layer on the gate electrode, a plurality of charge trapping layers on the blocking layer, a tunneling layer on the plurality of charge trapping layers, and a plurality of channel layers on the tunneling layer. The plurality of charge trapping layers are discrete and disposed at different levels. The plurality of channel layers are discrete and disposed at different levels. Each of the channel layers corresponds to a respective one of the charge trapping layers.”

The patent application was filed on December 26, 2019 (16/727,872).

Programming 3D memory device and related 3D memory
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,127,464) developed by Yang, Xue Peng, and You, Kaikai, Wuhan, China, for “method of programming 3D memory device and related 3D memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In a channel-stacked memory device which includes a first channel stacked on a second channel, the first channel is programmed in a bottom-to-top direction and the second channel is programmed in a top-to-bottom direction. The electrons in the first channel may be drained by a bit line, while the electrons in the second channel may be drained by a well region.”

The patent application was filed on March 23, 2020 (16/827,682).