R&D: Highly Available Packet Buffer Design With Hybrid Nonvolatile Memory

IEEE Transactions on Very Large Scale Integration (VLSI) Systems has published an article written by Yongwoon Song, Sogang University, Seoul, Republic of Korea, Jooyoung Hwang, Insoon Jo, Samsung Electronics Company Ltd., Hwaseong-si, Republic of Korea, and Hyukjun Lee, Sogang University, Seoul, Republic of Korea.

Abstract: “Internet routers/switches are vulnerable to system failures which require a power reset. Tremendous efforts are made to guarantee the high availability of the systems. A recent work shows that a phase change memory (PCM)-based routing lookup table can achieve high availability in the destination lookup of routers/switches. However, a packet buffer in routers/switches cannot benefit from the lookup table approach because it requires a much larger and higher-bandwidth memory system and its memory traffic is equally divided into reads and writes, while routing table accesses are mostly read-dominant. PCM can provide high availability even when the system undergoes a power reset but exhibits unacceptable write bandwidth. In this work, we propose a magnetic RAM (MRAM)/PCM-based hybrid memory packet buffer and a packet mapping method. A small MRAM combined with a large PCM can outperform the dynamic random access memory (DRAM)-based packet buffer by 28.5% or 22.4% on average for internet-mix packet traffic when optimizing only bandwidth or both bandwidth and lifetime. The proposed adaptive packet mapping method maps small packets less than a predetermined packet size threshold to MRAM for maximizing PCM bandwidth as small packets degrade row buffer locality in PCM. In addition, the mapping method dynamically changes the packet size threshold to capture the working set of packet buffering, which significantly improves PCM lifetime.“