PetaIO Assigned Three Patents

Asymmetric data striping for uneven NAND defect distribution
PetaIO Inc., Santa Clara, CA, has been assigned a patent (11,023,154) developed by Yoon, Jongman, San Jose, CA, for an “asymmetric data striping for uneven NAND defect distribution.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage device implements striping logic with respect to a plurality of slices, each slice including one or more storage media, such as NAND flash dies. Data operations are distributed among the slice in an unequal manner such that the frequency of selection of a slice decreases with number of defects in the NAND dies of that slice. For example, data operations may be distributed in a round-robin fashion with some slices being skipped periodically. In some embodiments, a skip map may be used that maps host addresses (HLBA) to a particular slice and device address (DLBA) in that slice, the skip map implementing the skipping of slices. The skip map may be smaller than the size of the storage device such that each HLBA is mapped to a zone of the storage device and a slice and offset within that zone are determined according to the skip map.”

The patent application was filed on October 10, 2018 (Appl. No.16/156,929).

Bit flipping algorithm for decoding LDPC-encoded data
PetaIO Inc., Santa Clara, CA, has been assigned a patent (10,965,319) developed by Zeng, LingQi, San Jose, CA, for a “bit flipping algorithm for decoding LDPC-encoded data.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A bit flipping algorithm for an LDPC decoder evaluates a data sequence d with respect to a parity code matrix H. Where one or more checks fail, bits of d are flipped such that for some iterations, the bits are flipped with bias toward and original data sequence r. For example, for some iterations, where the number of failed checks are below a first threshold T1, bits are only permitted to flip back to the value of that bit in the original data sequence r. In such iterations, bits are permitted to flip from the value in the original data sequence r only when the number of failed checks is greater than a second threshold T2, T2>T1. Values for thresholds may be based on a number of flipped bits from a previous iteration and may be calculated using a syndrome s=Hd from a previous iteration.”

The patent application was filed on October 25, 2018 (Appl. No.16/171,008).

QoS assisted AES engine for SSD controller
PetaIO Inc., Santa Clara, CA, has been assigned a patent (10,855,444) developed by Yang, Fan, Fremont, CA, and Ganesan, Aditi Rema, San Jose, CA, for a “QoS assisted AES engine for SSD controller.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A flow controller selects a direction (encryption/decryption) for an AES core according to quality of service parameters and a number of data words in encryption and decryption data buffers. A direction ratio may be calculated as a function of the quality of service parameters and the number of data words in the encryption and decryption data buffers. The flow controller selects the direction to reduce a cost function. The cost function may be at a minimum when a ratio of words in the encryption and decryption data buffers is the same as the direction ratio. A key management unit supplies keys according to the selected direction to the AES cores. Multiple AES cores may be used.”

The patent application was filed on October 24, 2018 (Appl. No.16/169,433).