R&D: Error Source and Latency-Aware Read Performance Optimization Scheme for Aged SSDs

IEICE Electronics Express has published an article written by Shiqiang Nie, Chi Zhang, Chen Zhang, Xuda Zheng, Weiguo Wu, Dept. of Computer Science and Technology, Xi’an Jiaotong University.

Abstract: “LDPC code has been used widely in NAND flash-based storage system due to its high error correction capacity, prolonging the lifetime of multi-bit NAND flash. However, the LDPC decoding latency degrades the read performance of SSD as it induces more read-retry operations. The last RL(Read-Level) recording method has been proposed in recent research works, which achieves better performance improvement by reducing many useless fail reads. However, these schemes reset the RL of these pages to be 1 after these blocks are erased. Using RL 1 to read these pages may induce many fail reads at first read on each page. That because it ignores the different error source issues, i.e., a part of the page error comes from the P/E cycles, while others come from retention time and other sources. Motivated by this observation, in this paper, we propose two schemes to optimize the read procedure of NAND flash-based SSD, especially for aged SSDs. We propose to record RL induced by different error sources separately, so the RL of the page could keep unchanged rather than 1 after the blocks are erased. The scheme could reduces useless fail read after the blocks are read at first time. We also design a latency aware I/O scheduler to reorder the input read requests in batch by prioritizing requests with low latency to reduce the queue latency. Our experiments show that the proposed scheme can reduce the average response time by up to 33% with less storage overhead.“