R&D: Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

IEEE Xplore has published, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems proceedings, an article written by John Reuben, Chair of Computer Architecture, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), 91058 Erlangen, Germany, and Stefan Pechmann, Chair of Communications Electronics, Universität Bayreuth, 95447 Bayreuth, Germany.

Abstract: “To overcome the ‘von Neumann bottleneck,’ methods to compute in memory are being researched in many emerging memory technologies, including resistive RAMs (ReRAMs). Majority logic is efficient for synthesizing arithmetic circuits when compared to NAND/NOR/imply logic. In this work, we propose a method to implement a majority gate in a transistor-accessed ReRAM array during the READ operation. Together with not gate, which is also implemented in memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. While many methods have been proposed recently to implement the Boolean logic in memory, the latency of in-memory adders implemented as a sequence of such Boolean operations is exorbitant (O(n)). Parallel-prefix (PP) adders use prefix computation to accelerate addition in conventional CMOS-based adders. By exploiting the parallel-friendly nature of the proposed majority gate and the regular structure of the memory array, it is demonstrated how PP adders can be implemented in memory in O(log(n)) latency. The proposed in-memory addition technique incurs a latency of 4·log(n)+6 for n-bit addition and is energy-efficient due to the absence of sneak currents in 1Transistor-1Resistor configuration.“