R&D: Energy-Efficient Hybrid Tunnel FET Based STT-MRAM Memory Cell Design at Low VDD

International Journal of Electronics has published an article written by Sudha Vani Yamani, N Usha Rani, Department of Electronics and Communication Engineering, Vignan’s Foundation of Science Technology and Research, Guntur, India, and Ramesh vaddi, Department of Electronics and Communication Engineering, School of Engineering and Applied Sciencs, SRM University, Amaravati, India.

Abstract: “Perpendicular Magnetic Anisotropy based Magnetic Tunnel Junction (PMA-MTJ), Spin Transfer Torque Magnetic Random-Access Memory (STT-MRAM) has attracted wide attention among the next generation Non-Volatile Memory (NVM) technologies due to low leakage and high-density characteristics for embedded memory architectures. However, STT-MRAM based memory cells are not energy efficient with CMOS scaling at scaled supply Voltages. This paper presents a novel energy-efficient Hybrid TFET (1T: Hetero-junction TFET, 1T: Homo-junction TFET)/STT-MRAM cell that explores p-i-n forward current of Tunnel FET. The proposed hybrid memory cell demonstrates ~27.3% energy efficiency over equivalent 1T FinFET/STT-MRAM cell, 16.75% energy efficiency over equivalent 1T Homo-junction TFET/STT-MRAM cell and 24.3% energy efficiency over equivalent 1T Hetero-junction TFET/STT-MRAM cell at V_DD=0.5V.“