R&D: Novel Method of Overlay Variation Study for 3D NAND Channel Hole

SPIE has published, in Proceedings Volume 11611, Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV, an article written by Leeming Tu, Haydn zhou, Yangtze Memory Technologies Co., Ltd., China, Erik Xiao, Jin Zhu, Cynthia Li, Ningqi Zhu, Xin Li, Jason Pei, Miao Bing, Seddy Chu, KLA Corp., China, Kevin Huang, KLA Corp., USA, Bob Dong, KLA Corp., China.

Abstract: “In recent years, the pursuit of high storage capacity in 3D-NAND flash devices has driven the addition of more layers to increase the stack height. Challenges arise when etching high aspect ratio memory holes. Due to the existence of a thick and opaque hard mask layer, overlay control faces significant lot-to-lot variation and difficulty of run-to-run feedback control. In this paper, a fundamental study on channel hole overlay variation is revealed by collecting and analyzing step-by step overlay, etch tilt and stress data. The strong correlation between overlay/tilt/stress identifies the main contributor of overlay lot-to-lot variation to be from etch tilt, which also strongly correlates to etch chamber RF hour (accumulated hours the chamber has run since its last PM event) without chamber dependency. In addition, overlay simulations showed lots grouped by RF hour can effectively reduce lot-to-lot overlay variation.“