Micron Assigned Twenty-Three Patents

Recovery of memory from asynchronous power loss
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,872,639) developed by Luo, Xiangang, Fremont, CA, Huang, Jianmin, San Carlos, CA, Fumagalli, Patroclo, Carate Brianza, Italy, Stoller, Scott Anthony, Boise, ID, Magnavacca, Alessandro, Sesto San Giovanni, Italy, and Pozzato, Andrea, Paderno Dugnano, Italy, for “recovery of memory from asynchronous power loss.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of zeros in the first physical page.”

The patent application was filed on August 29, 2019 (16/555,508).

Managing redundancy contexts in storage devices using eviction and restoration
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,872,039) developed by Crowley, James P., Longmont, CO, Pavlenko, Yuriy, Lake Forest, CA, and Schuh, Karl D., Santa Cruz, CA, for “managing redundancy contexts in storage devices using eviction and restoration.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A controller selects a redundancy context for eviction in response to a request for a redundancy context. The redundancy context includes buffer data and an identifier. The redundancy context is evicted by instructing a redundancy component to send the buffer data and identifier to a memory component to store in a buffer as an evicted context. The controller instructs the memory component to provide the evicted context for storage in a controller buffer. A new redundancy context is allocated to the requester following the eviction.”

The patent application was filed on December 3, 2018 (16/208,499).

Data recovery after storage failure in memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,872,008) developed by Crowley, James P., and Sheperek, Michael W., Longmont, CO, for a “data recovery after storage failure in a memory system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Exemplary methods, apparatuses, and systems include a memory controller receiving a first physical address corresponding to a logical address and data and initiating storage of the data at the first physical address. The memory controller sends a message indicating that the data has been successfully stored at the first physical address before determining if the data was successfully stored at the first physical address. Upon determining that the data failed to store at the first physical address, the memory controller retrieves the data from a volatile memory associated with the first physical address. The memory controller sends a request and receives a second physical address for the retrieved data. The memory controller initiates storage of the data at the second physical address.”

The patent application was filed on June 22, 2018 (16/016,456).

Subarray addressing
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,867,662) developed by Hush, Glen E., and Murphy, Richard C., Boise, ID, for “apparatuses and methods for subarray addressing.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems, apparatuses and methods related to subarray addressing for electronic memory and/or storage are described. Concurrent access to different rows within different subarrays may be enabled via independent subarray addressing such that each of the subarrays may serve as a ‘virtual bank.’ Accessing the different rows as such may provide improved throughput of data values accessed from the respective rows being sent to a destination location. For instance, one such apparatus includes a plurality of subarrays within a bank of a memory device. Circuitry within the bank is coupled to the plurality of subarrays. The circuitry may be configured to activate a row at a particular ordinal position in a first subarray during a time period and a row at a different ordinal position in a second subarray of the plurality of subarrays during the same time period.”

The patent application was filed on August 29, 2019 (16/555,012).

Providing data to configurable storage area
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,860,482) developed by Mirichigni, Graziano, Vimercate, Italy, Porzio, Luca, Volla, Italy, Di Martino, Erminio, Quarto, Italy, Bernardi, Giacomo, Marcianise, Italy, Monteleone, Domenico, Caserta, Italy, Zanardi, Stefano, Seriate, Italy, Tan, Chee Weng, Jurong West, Singapore, LeMarie, Sebastien, Singapore, Singapore, and Klindworth, Andre, Neubiberg, Germany, for “apparatuses and methods for providing data to a configurable storage area.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatuses and methods for providing data to a configurable storage area are described herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.”

The patent application was filed on February 11, 2019 (16/272,945).

Multilevel addressing
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,860,474) developed by Ferrante, Gianfranco, San Giorgio A Cremano, Italy, and Minopoli, Dionisio, Arzano, Italy, for a “multilevel addressing.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”In an example, a starting address corresponding to a location of particular information within a non-volatile storage memory is determined during an initialization process using a multilevel addressing scheme. Using the multilevel addressing scheme may include performing multiple reads of the storage memory at respective address levels to determine the starting address corresponding to the location of the particular information.”

The patent application was filed on December 14, 2017 (15/841,378).

Dopant-modulated etching for memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,854,813) developed by Tortorelli, Innocenzo, Cernusco sul Naviglio, Italy, and Robustelli, Mattia, Milan, Italy, for a “dopant-modulated etching for memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Methods and devices based on the use of dopant-modulated etching are described. During fabrication, a memory storage element of a memory cell may be non-uniformly doped with a dopant that affects a subsequent etching rate of the memory storage element. After etching, the memory storage element may have an asymmetric geometry or taper profile corresponding to the non-uniform doping concentration. A multi-deck memory device may also be formed using dopant-modulated etching. Memory storage elements on different memory decks may have different taper profiles and different doping gradients.”

The patent application was filed on February 9, 2018 (15/893,110).

NAND memory arrays
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,854,747) developed by Carlson, Chris M., Nampa, ID, Liu, Hung-Wei, Meridian, ID, Li, Jie, and Pavlopoulos, Dimitrios, Boise, ID, for “NAND memory arrays, devices comprising semiconductor channel material and nitrogen, and methods of forming NAND memory arrays.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays.”

The patent application was filed on May 15, 2019 (16/412,710).

Cross-point memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,854,675) developed by Sciarrillo, Samuele, Lomagna, Italy, for “cross-point memory and methods for fabrication of same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls.”

The patent application was filed on August 15, 2019 (16/542,136).

Cross-point memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,854,674) developed by Ravasio, Marcello, Olgiate Molgora, Italy, Sciarrillo, Samuele, Pellizzer, Fabio, Boise, ID, Tortorelli, Innocenzo, Cernusco sul Naviglio, Italy, Somaschini, Roberto, Vimercate, Italy, Casellato, Cristina, Sulbiate, Italy, and Mottadelli, Riccardo, Verano Brianza, Italy, for “cross-point memory and methods for fabrication of same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.”

The patent application was filed on August 31, 2017 (15/693,102).

Compute components formed over array of memory cells
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,854,269) developed by Zawodny, Jason T., Grand Rapids, MI, for “apparatuses and methods for compute components formed over an array of memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The present disclosure includes apparatuses and methods related to compute components formed over an array of storage elements. An example apparatus comprises a base substrate material and an array of memory cells formed over the base substrate material. The array can include a plurality of access transistors comprising a first semiconductor material. A compute component can be formed over and coupled to the array. The compute component can include a plurality of compute transistors comprising a second semiconductor material. The second semiconductor material can have a higher concentration of doping ions than the first semiconductor material.”

The patent application was filed on July 30, 2019 (16/526,198).

Key-value store using journaling with selective storage format
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,852,978) developed by Kurichiyath, Sudheer, Becker, Greg A., Boles, David, Austin, TX, Moyer, Steven, Round Rock, TX, Meeramohideen Mohamed, Nabeel, and Tomlinson, Alexander, Austin, TX, for a “key-value store using journaling with selective data storage format.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Aspects of the present disclosure provide for operations of a key-value store (KVS) that uses journaling with storage of data (e.g., key data or value data of a key-value pair) in different types of data storage objects (e.g., data storage formats) selected based on one or more criteria.”

The patent application was filed on December 14, 2018 (16/220,646).

Predictive data pre-fetching in storage device
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,852,949) developed by Frolikov, Alex, Vogel, Zachary Andrew Pete, San Jose, CA, Mendes, Joe Gil, Santa Cruz, CA, and Guda, Chandra Mouli, San Jose, CA, for a “predictive data pre-fetching in a data storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage system having non-volatile media, a buffer memory, a processing device, and a data pre-fetcher. The data pre-fetcher receives commands to be executed in the data storage system, provides the commands as input to a predictive model, obtains at least one command identified for pre-fetching, as output from the predictive model having the commands as input. Prior to the command being executed in the data storage device, the data pre-fetcher retrieves, from the non-volatile memory, at least a portion of data to be used in execution of the command, and stores the portion of data in the buffer memory. The retrieving and storing the portion of the data can be performed concurrently with the execution of many commands before the execution of the command, to reduce the latency impact of the command on other commands that are executed concurrently with the execution of the command.”

The patent application was filed on April 15, 2019 (16/384,618).

Forming array of elevationally-extending strings of memory cells
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,847,538) developed by Howder, Collin, Meridian, ID, Meyer, Ryan M., and Carter, Chet E., Boise, ID, for “methods of forming an array of elevationally-extending strings of memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method of forming an array of elevationally-extending strings of memory cells comprises forming conductively-doped semiconductor material directly above and electrically coupled to metal material. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed directly above the conductively-doped semiconductor material. Horizontally-elongated trenches are formed through the stack to the conductively-doped semiconductor material. The conductively-doped semiconductor material is oxidized through the trenches to form an oxide therefrom that is directly above the metal material. Transistor channel material is provided to extend elevationally along the alternating tiers. The wordline tiers are provided to comprise control-gate material having terminal ends corresponding to control-gate regions of individual memory cells. Charge-storage material is between the transistor channel material and the control-gate regions. Insulative charge-passage material is between the transistor channel material and the charge-storage material. A charge-blocking region is between the charge-storage material and individual of the control-gate regions.”

The patent application was filed on February 11, 2019 (16/272,547).

Black box data recorder for autonomous driving vehicle
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,846,955) developed by Golov, Gil, Backnang, Germany, for a “black box data recorder for autonomous driving vehicle.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An improved black box data recorder for use with autonomous driving vehicles (AVD). In one embodiment, two cyclic buffers are provided to record vehicle sensors data. A first cyclic buffer records raw vehicle sensor data on a volatile memory, while a second cyclic buffer records the same vehicle sensor data, as compressed data, on a non-volatile memory. In a case of a collision or near collision, in one embodiment the buffers are flushed into a non-volatile (NV) storage for retrieval. As long as there is no power interruption, the raw vehicle sensor data will be accessible from the NV storage. If a power interruption occurs, the raw vehicle sensor data held in the volatile memory of the first cyclic buffer will be lost and only the compressed form of the vehicle sensor data from the NV second cyclic buffer will survive and be accessible.”

The patent application was filed on March 16, 2018 (15/923,820).

Persistent content in nonvolatile memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,846,215) developed by Hulbert, Jared E., Cameron Park, CA, Rudelic, John C., Folsom, CA, and Wang, Hongyu, Shanghai, China, for a “persistent content in nonvolatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Applications may request persistent storage in nonvolatile memory. The persistent storage is maintained across power events and application instantiations. Persistent storage may be maintained by systems with or without memory management units.”

The patent application was filed on December 20, 2018 (16/227,339).

Storing parity data mid stripe
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,838,812) developed by Boals, Daniel A., Broomfield, CO, for “storing parity data mid stripe.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”User data to be stored at a data block location of a plurality of data block locations at a storage system may be received. A parity data based on the received user data may be generated. An indication of an occurrence of an event associated with the storage system may be received. In response to receiving the indication of the occurrence of the event, the parity data may be stored by a processing device at a particular data block location of the plurality of data block locations where the particular data block location is situated prior to another data block location, of the plurality of data block locations, that is to store another parity data based on a subsequent user data.”

The patent application was filed on November 13, 2018 (16/190,006).

Status management in storage backed memory package
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,838,637) developed by Burns, Michael, Maple Grove, MN, Van Sickle, Gary R., Arden Hills, MN, and Leyda, Jeffery J., Minneapolis, MN, for “status management in storage backed memory package.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Devices and techniques for status management in storage backed memory are disclosed herein. An encoded message can be received at a first interface of the memory package. Here, the memory package also includes a second interface to a host. The message can be decoded to obtain a decoded message that includes an attribute. The attribute can be compared a set of attributes that correspond to an advertised status of the memory package. The comparison enables a determination that the attribute is in the set of attributes. The advertised status of the memory package can then be modified in response to the determination that the attribute is in the set of attributes.”

The patent application was filed on August 3, 2018 (16/054,144).

Storage based on data polarity
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,832,768) developed by Schreck, John F., Lucas, TX, and Raad, George B., Boise, ID, for a “data storage based on data polarity.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Methods, systems, and devices for storing and reading data at a memory device are described. A memory device may utilize one or more storage states to store data within a data word. The memory device may exhibit higher data leakage or more power consumption when storing or reading a first storage state compared to storing or reading one or more other storage states. In some cases, the memory device may generate a second data word corresponding to a first data word by modifying each symbol type of the first data word to generate a different symbol type for the second data word. A memory device may reduce the occurrence of a storage state associated with large data leakage, or high-power consumption, or both. Further, the memory device may generate and store an indicator indicating the transformation of a corresponding data word.”

The patent application was filed on July 1, 2019 (16/459,462).

Multi-decks memory device including inter-deck switches
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,825,523) developed by Li, Benben, Goda, Akira, Abdelrahaman, Ramey M., Laboriante, Ian C., Boise, ID, and Parat, Krishna K., Palo Alto, CA, for a “multi-decks memory device including inter-deck switches.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.”

The patent application was filed on October 29, 2019 (16/667,465).

Managed NAND data compression
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,824,371) developed by Jean, Sebastien Andre, Meridian, ID, for a “managed NAND data compression.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatus and methods are disclosed, including providing available data operations for the storage system processor to a host processor, identifying data operations to be performed by the storage system processor, and assigning identified data operations to the storage system processor to reduce bus traffic between the host processor and the storage system processor, to improve host processor performance, and to reduce energy use by the host processor.”

The patent application was filed on June 19, 2018 (16/012,750).

Storage node shaping
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,811,419) developed by Shreeram, Devesh Dadhich, Kelkar, Sanket S., Lugani, Gurpreet S., Paduano, Paul A., Rocklein, Matthew N., Sapra, Sanjeev, and Petz, Christopher W., Boise, ID, for a “storage node shaping.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Methods, apparatuses, and systems related to shaping a storage node material are described. An example method includes forming a pillar with a pattern of materials. The method further includes depositing a storage node material on a side of the pillar. The method further includes etching sacrificial materials within the pillar. The method further includes etching the storage node material in a direction from the pillar into the storage node.”

The patent application was filed on May 22, 2019 (16/419,730).

Client-assisted phase-based media scrubbing
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,810,097) developed by Bradshaw, Samuel E., Sacramento, CA, and Eno, Justin, El Dorado Hills, CA, for a “client-assisted phase-based media scrubbing.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A technique of receiving a write transaction directed to a group of memory parcels of a memory device from a client source. The technique determines a state of a first indicator used to indicate which one of two data structures contains a newer mapping of the group of memory parcels, while the other data structure contains an older mapping of the group of memory parcels. The technique determines a state of a second indicator used to indicate which one of the two data structures is in current use for the group of memory parcels and compares the states of the two indicators. When a data structure in current use does not contain the newer mapping, the technique changes the state of the second indicator to the state of the first indicator. The technique writes content of the write transaction to storage locations based on the newer mapping.”

The patent application was filed on November 7, 2018 (16/183,628).

Folding device stand for portable devices
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,798,840) developed by Hoem, Sophia, San Jose, CA, and Brewer, Wesley G., Menlo Park, CA, for a “folding device stand for portable devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A device stand for a portable device, comprising a foldable extension leg which supports the portable device at a cable connection instead of directly supporting the portable device itself. In one or more embodiments, the device stand can be connected to a storage device such as a flash drive, or can directly incorporate a storage device into its form.”

The patent application was filed on March 14, 2017 (15/458,516).

Multiple memory type memory module
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,789,177) developed by Murphy, Richard C., Boise, ID, for “multiple memory type memory module systems and methods.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The present disclosure provides methods, apparatuses, and systems for implementing and operating a memory module, for example, in a computing device that includes a network interface, which is coupled to a network to enable communication with a client device, and processing circuitry, which is coupled to the network interface via a data bus and programmed to perform operations based on user inputs received from the client device. The memory module includes memory devices, which may be non-volatile memory or volatile memory, and a memory controller coupled between the data bus and the of memory devices. The memory controller may be programmed to determine when the processing circuitry is expected to request a data block and control data storage in the memory devices.”

The patent application was filed on July 20, 2018 (16/041,493).

Mixed cross point memory
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,777,266) developed by Redaelli, Andrea, Casatenovo, Italy, Tortorelli, Innocenzo, Cernusco sul Naviglio, Italy, Pirovano, Agostino, Milan, Italy, and Pellizzer, Fabio, Boise, ID, for a “mixed cross point memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a self-selecting memory element and another array with a cell having a memory storage element and a selector device. The device may be programmed to store multiple combinations of logic states using cells of one or more decks. Both the first deck and second deck may be coupled to at least two access lines and may have one access line that is a common access line, coupling the two decks. Additionally, both decks may overlie control circuitry, which facilitates read and write operations. The control circuitry may be configured to write a first state or a second state to one or both of the memory decks via the access lines.”

The patent application was filed on November 9, 2018 (16/185,146).

Extended error correction in storage device
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,776,201) developed by Palmer, David Aaron, Boise, ID, for an “extended error correction in storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Devices and techniques for extended error correction in a storage device are described herein. A first set of data, that has a corresponding logical address and physical address, is received. A second set of data can be selected based on the logical address. Secondary error correction data can be computed from the first set of data and the second set of data. Primary error correction data can be differentiated from the secondary error correction data by being computed from the first set of data and a third set of data. The third set of data can be selected based on the physical address of the first set of data. The secondary error correction data can be written to the storage device based on the logical address.”

The patent application was filed on December 28, 2018 (16/236,094).

Allocation of storage connection resources
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,747,441) developed by Jean, Sebastien Andre, Meridian, ID, for an “efficient allocation of storage connection resources.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Devices and techniques for efficient allocation of storage connection resources are disclosed herein. An active trigger for a storage device is received when the storage device is in an idle state. A workload that corresponds to the storage device is measured to determine that the workload meets a threshold. Connection parameters, for a connection to the storage device, are negotiated based on the workload in response to receipt of the active trigger and the workload meeting the threshold. The workload is then executed on the storage device via the connection using the connection parameters.”

The patent application was filed on August 30, 2017 (15/690,992).

Memory devices including gettering agents in memory charge storage structures
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,734,491) developed by Brewer, Rhett T., Santa Clara, CA, and Ramaswamy, Durai V., Boise, ID, for “memory devices including gettering agents in memory charge storage structures.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Memory devices might include an array of memory cells and a control logic to control access of the array of memory cells, where a memory cell of the array of memory cells might include a first dielectric adjacent a semiconductor, a control gate, a second dielectric between the control gate and the first dielectric, and a charge storage structure between the first dielectric and the second dielectric, wherein the charge storage structure comprises a charge-storage material and a gettering agent.”

The patent application was filed on August 8, 2018 (16/057,998).