Western Digital Assigned Twenty-One Patents

Reducing vibration of data storage device in data storage
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,593,370) developed by Xiong, Shaomin, Fremont, CA, Hirano, Toshiki, Yamamoto, Satoshi, San Jose, CA, Wilke, Jeff, Palmer Lake, CO, and Niss, Dave, Boulder, CO, for “reducing vibration of data storage device in a data storage system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage system may include multiple data storage devices, such as hard disk drives, a cooling fan, and a sound balancer structure between the fan and the drives. The sound balancer is intentionally positioned where it substantially balances, about the center of rotation of and along at least one axis of a fan-facing storage device, the sound pressure from the fan that impinges upon the fan-facing face of the storage device. This redistribution of the sound pressure suppresses sound pressure-induced torque upon and therefore rotational vibration of the storage device, which in turn enhances the track following capability of the storage device.”

The patent application was filed on November 6, 2018 (16/182,447).

Data storage device emphasizing parity sector processing of un-converged codewords
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,592,334) developed by Oboukhov, Iouri, Ravindran, Niranjay,and Galbraith, Richard L., Rochester, MN, for a “data storage device emphasizing parity sector processing of un-converged codewords.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device is disclosed comprising a non-volatile storage medium (NVSM) wherein a plurality of codewords and corresponding parity sector are written to the NVSM and then read from the NVSM. Each codeword read from the NVSM is processed using a Viterbi-type detector, thereby generating codeword reliability metrics. The codeword reliability metrics for at least some of the codewords are processed using a low density parity check (LDPC) type decoder, thereby generating a LDPC reliability metric for each symbol of at least one codeword. The LDPC reliability metrics for at least one of an un-converged codeword are processed using the parity sector, thereby updating the un-converged codeword reliability metrics. Processing the codeword reliability metrics with the LDPC decoder and updating the reliability metrics with the parity sector is repeated at least once before updating the LDPC reliability metrics of at least the un-converged codeword using the Viterbi-type detector.”

The patent application was filed on May 17, 2018 (15/983,016).

Storage system fabric with multichannel compute complex
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,592,144) developed by Roberts, Adam, Moncure, NC, Munnangi, Sivakumar, San Jose, CA, and Scaramuzzo, John, Los Gatos, CA, for a “storage system fabric with multichannel compute complex.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Example storage systems and methods provide multichannel communication among subsystems, including a compute complex. A plurality of storage devices, a host, and a compute complex are interconnected over an interconnect fabric. The storage system is configured with a host-storage channel for communication between the host and the plurality of storage devices, host-compute channel for communication between the host and the compute complex, and a compute-storage channel for communication between the compute complex and the storage devices.”

The patent application was filed on August 3, 2018 (16/054,980).

Error characterization for control of non-volatile memory
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,592,141) developed by Lakshmi, Vinay Vijendra Kumar, and Gopalakrishnan, Raghavendra, Bangalore, India, for an “error characterization for control of non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatuses, systems, and methods are disclosed for error characterization for control of non-volatile memory. An apparatus may include an array of non-volatile memory cells and a controller. A controller may be configured to acquire an error characterization for a region of memory. Also, an error characterization may comprise information about one or more types of errors to which a region of memory is susceptible. A controller may be configured to assign a region of memory into a logical group based on an error characterization. Further, a logical group may comprise a plurality of regions of memory. Additionally, a controller may be configured to service a write request by striping data across multiple regions assigned to a logical group.”

The patent application was filed on March 6, 2018 (15/913,898).

Data storage device with embedded software
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,587,689) developed by Malina, James N., Arul Dhas, Benixon, Irvine, CA, and Chen, Albert H., Redmond, WA, for a “data storage device with embedded software.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A Data Storage Device (DSD) includes a Non-Volatile Memory (NVM) for storing data and a first processor configured to execute a firmware for retrieving data from the NVM and storing data in the NVM. A second processor of the DSD executes an application Operating System (OS) to interface with the first processor. The second processor sends a command to the first processor using the application OS to retrieve data from the NVM or store data in the NVM.”

The patent application was filed on February 12, 2015 (14/621,314).

Storage device with debug namespace
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,580,512) developed by Subramanian, Karthik, and Lakshmi, Vinay Vijendra Kumar, Bangalore, India, for a “storage device with debug namespace.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An example of a system includes a host interface, a set of non-volatile memory cells assigned a first logical address range, and one or more control circuits coupled to the host interface and coupled to the set of non-volatile memory cells. The one or more control circuits are configured to generate debug data and send the debug data through the host interface in response to a command received through the host interface. The command is directed to a second logical address range, the second logical address range assigned exclusively for debug data.”

The patent application was filed on February 21, 2018 (15/901,054).

Adjusting read levels in storage device based on bias functions
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,580,485) developed by Avraham, Dudy, Even Yehuda, Israel, Bazarsky, Alexander, Holon, Israel, Eliash, Tomer Tzvi, Kfar Saba, Israel, Rozman, David, Kiryat-Malakhi, Israel, Sharon, Eran, Rishon Lezion, Israel, and Shulkin, Arthur, Yavne, Israel, for “system and method for adjusting read levels in a storage device based on bias functions.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Disclosed is a system and method for adjusting read levels in a storage device based on bias functions. The method includes receiving a request to perform a memory access operation on a wordline of non-volatile memory. The method also includes selecting a bias function corresponding to the wordline of the non-volatile memory from a group of bias functions. The method also includes determining a bias value based on the selected bias function and the wordline. The method also includes adjusting a read level in the non-volatile memory based on the bias value. The method also includes performing the memory access operation on the wordline of the non-volatile memory using the adjusted read level. The bias functions may be linear functions and adjusted in response to detecting a recalibration condition.”

The patent application was filed on December 20, 2017 (15/849,572).

Queue depth management for host systems accessing peripheral component interconnect express, (PCIe) device via PCIe switch
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,579,567) developed by Elkington, Susan, Colorado Springs, CO, Roberson, Randy, Lutz, FL, Hess, Randall, Stillwell, Michael, and Walker, Michael, Colorado Springs, CO, for “queue depth management for host systems accessing a peripheral component interconnect express, (PCIe) device via a PCIe switch.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Described herein are enhancements for managing quality of service in a multi-host Peripheral Component Interconnect Express (PCIe) switching environment. In one implementation, a host system is configured to maintain quality of service statistics corresponding to data interactions with a PCIe storage device available via a PCIe switch. The host system may further receive secondary quality of service statistics for one or more other host systems communicatively coupled to the PCIe device via the PCIe switch, and determine a maximum queue depth for the host system based on the quality of service statistics and the second quality of service statistics to maintain a quality of service for the host systems.”

The patent application was filed on June 28, 2017 (15/635,687).

Predicting addresses in non-volatile storage
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,579,538) developed by Marcu, Alon, Tel-Mond, Israel, Hahn, Judah Gamliel, Ofra, Israel, Benisty, Shay, Beer Sheva, Israel, Bazarsky, Alexander, Holon, Israel, and Navon, Ariel, Revava, Israel, for “predicting addresses in non-volatile storage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Memory systems that can predict a physical address associated with a logical address, and methods for use therewith, are described herein. In one aspect, the memory system predicts a physical address for a logical address that follows a sequence of random logical addresses. The predicted physical address could be a physical location where the data for the logical address is predicted to be stored. In some cases, the host data can be returned without accessing a management table. The predicted physical address is not required to be the location of the data to be returned to the host for the logical address. In one aspect, the memory system predicts a physical address at which information is stored that may be used to ultimately provide the data for the logical address, such as a location in the management table.”

The patent application was filed on February 21, 2018 (15/901,432).

Hermetic sealed electrical connector with high-speed transmission for hard disk drive
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,575,424) developed by Onobu, Yuta, Yokohama, Japan, Hayakawa, Takako, Hiratsuka, Japan, Sudo, Kimihiko, Yokohama, Japan, Choe, Seong-Hun, Nagata, Takehito, Fujisawa, Japan, Soga, Yuji, Ashigarakamigun Oimachi, Japan, Nishiyama, Nobumasa, Yokohama, Japan, and Nagaoka, Kazuhiro, Fujisawa, Japan, for a “hermetic sealed electrical connector with high-speed transmission for hard disk drive.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Embodiments disclosed herein generally relate to hermetic electrical connectors used in hard disk drives. The hermetic electrical connector includes a barrier structure having a first plurality of connecting pads disposed on a first surface of the barrier structure and a second plurality of connecting pads disposed on a second surface of the barrier structure opposite the first surface. A plurality of conductors is disposed within the barrier structure, and each conductor is coupled to a connecting pad of the first plurality of connecting pads and a corresponding connecting pad of the second plurality of connecting pads. The barrier structure further includes a dielectric material between the first and second surfaces, and one or more layers embedded in the dielectric material. The addition of the layers helps choke the helium gas flow, thus improving sealing of the electrical connector while maintaining high-speed electrical transmission.”

The patent application was filed on February 20, 2017 (16/086,513).

Parameter tracking for non-volatile memory to avoid over-programming
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,573,397) developed by Sehgal, Rohit, Sharma, Sahil, San Jose, CA, Reusswig, Philip, and Yang, Nian Niles, Mountain View, CA, for a “parameter tracking for non-volatile memory to avoid over-programming.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”On a non-volatile memory circuit, peripheral circuitry generates programming voltages based on parameter values. If parameter values are incorrectly translated into programming voltages, data may be over-programmed, resulting in high bit error rates (BERs). The memory system can monitor the error rates using memory cell voltage distributions for different portions of the memory and look for signatures of such incorrect implementation. For example, by monitoring the BER along word lines that are most prone to error due to incorrectly implemented programming parameters, the memory system can determine if the programming parameters for the corresponding portion of a memory device indicate such anomalous behavior. If such a signature is found, the memory system checks to see whether the programming parameters should be adjusted, such as by comparing the programming parameters used on one die to programming parameters used on another die of the memory system, and adjust the programming parameters accordingly.”

The patent application was filed on December 4, 2018 (16/209,519).

Non-volatile storage with adjustable select gates as function of temperature
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,573,388) developed by Gupta, Mahim Raj, Milpitas, CA, Purahmad, Mohsen, Sunnyvale, CA, Lei, Bo, San Ramon, CA, Lai, Joanna, and Costa, Xiying, San Jose, CA, for a “non-volatile storage system with adjustable select gates as a function of temperature.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A non-volatile storage system comprises memory cells arranged in groups of memory cells that include programmable select gates and one or more control circuits in communication with the memory cells. The one or more control circuits configured to identify a select gate that needs to be programmed and program the select gate identified to be programmed if a temperature at the non-volatile memory cells is greater than a minimum temperature and defer programming of the select gate identified to be programmed until the temperature at the non-volatile memory cells is greater than the minimum temperature. In some embodiments, the one or more control circuits are configured to perform dummy memory operations on the plurality of non-volatile memory cells to raise the temperature of the non-volatile memory cells in response to determining that the temperature at the non-volatile memory cells is not high enough.”

The patent application was filed on April 4, 2018 (15/944,917).

Hybrid data storage array
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,572,407) developed by Xu, Jun, Niu, Junpeng, Singapore, Singapore, Boyle, William Bernard, Lake Forest, CA, and Yu, Jie, Irvine, CA, for a “hybrid data storage array.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage system may include one or more storage arrays. Each storage array may include a first set of solid-state drives and a first set of striped hard disk drives. Each solid-state drive of the first set of solid-state drives has a first data throughput and the set of stripe hard disk drives has a second data throughput. The second data throughput of the first set of striped hard disk drives is within a threshold throughput of the first data throughput. The data storage system also includes a processing device configured to receive an access request to write first data to the storage array and determine a read access frequency of the first data. The processing device may also be configured to determine a write access frequency of the first data and write the first data to the first set of solid-state drives or the first set of striped hard disk drives, based on the read access frequency and the write access frequency.”

The patent application was filed on August 11, 2017 (15/675,018).

Implementing logical to physical address mapping in SSD
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,572,391) developed by Modi, Anshul, Kavirayani, Chaitanya, Dubey, Rishabh, Raja Murthy, Sampath, Bangalore, India, Kumar, Satish, Chennai, India, and Sivasankaran, Vijay, Bangalore, India, for “methods and apparatus for implementing a logical to physical address mapping in a solid state drive.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Aspects of the disclosure provide for managing a logical to physical (L2P) table in a Solid State Drive (SSD). Methods and apparatus provide for using a non-volatile memory (NVM) to store the L2P table in its entirety, where the L2P table is separated into a plurality of partitions. The SSD is partitioned into front and back-end processing portions where a partition table is managed by the back-end portion and includes one or more addresses of partitioned portions of the plurality partitions of the L2P table stored in the NVM. The back-end processing portion receives requests from the host via the front-end processing portion and accesses the partition table for scheduling read or write access to the NVM by determining one or more addresses of the respective partitioned portions of the plurality partitions of the L2P table stored in the NVM from the partition table.”

The patent application was filed on February 9, 2018 (15/893,392).

Data management in RAID environment
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,572,358) developed by Spongr, John, Rancho Santa Margarita, CA, for a “data management in RAID environment.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage system includes a plurality of Data Storage Devices (DSDs) having a total storage capacity available for storing user data among the plurality of DSDs. Each DSD of the plurality of DSDs has a DSD storage capacity that contributes to the total storage capacity of the plurality of DSDs. A strip size is assigned to each DSD of the plurality of DSDs based at least in part on a portion of the total storage capacity that is contributed by the DSD storage capacity of the respective DSD. Data is received for storage in a data stripe across the plurality of DSDs and the data stripe is stored across the plurality of DSDs such that each DSD of the plurality of DSDs stores a different portion of the data stripe having the strip size assigned to the DSD.”

The patent application was filed on June 16, 2015 (14/741,287).

Non-volatile storage with command replay
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,572,185) developed by Hahn, Judah Gamliel, Ofra, Israel, and Benisty, Shay, Beer Sheva, Israel, for a “non-volatile storage system with command replay.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory system includes a non-volatile memory and a controller connected to the non-volatile memory. The controller is configured to receive a set of commands from a host during a first host startup sequence, write the set of commands in the non-volatile memory, and in response to receiving an indicator from the host, execute the set of commands written in the non-volatile memory during a second host startup sequence.”

The patent application was filed on June 1, 2018 (15/995,590).

Scheduling scheme(s) for multi-die storage device
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,572,169) developed by Frid, Marina, Jerusalem, Israel, Genshaft, Igor, Bat Yam, Israel, Zevulun, Einat Inna, Kfar Saba, Israel, Duzly, Yacov, Ra’anana, Israel, and Shaharabany, Amir, Kochav Yair, Israel, for “scheduling scheme(s) for a multi-die storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A device includes a schedule engine including a mode selection input. The schedule engine has an operating mode based on the mode selection input. The operating mode includes an opportunistic scheduling mode based on the mode selection input having a first value and a pipelined scheduling mode based on the mode selection input having a second value. The device further includes a buffer coupled to the schedule engine.”

The patent application was filed on January 22, 2018 (15/876,253).

Efficient data management through compressed data interfaces
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,572,153) developed by Singhai, Ashish, Los Altos, CA, Battaje, Ajith Kumar, Sharma, Sandeep, Karnataka, India, and Manchanda, Saurabh, Delhi, India, for an “efficient data management through compressed data interfaces.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A system and method for efficiently managing data through compression interfaces may include receiving, by a controller, data, generating, by the controller, a compressed payload based on the data, generating, by the controller, metadata describing the compressed payload, the metadata including fixed size metadata and variable size metadata, generating, by the controller, a data container comprising the uncompressed payload and the metadata, and transmitting, by the controller, the data container to an application. Some implementations of the system may include a storage media, and a storage controller executable by a processor that may include an interface processor, a controller logic, and a media processor configured to communicate with an application and the storage media to perform aspects of the method.”

The patent application was filed on June 13, 2017 (15/621,960).

Data storage device reverse biasing head element to counter electro-migration
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,566,018) developed by Poss, Joey M., Rochester, MN, McFadyen, Ian R., Luo, Jih-Shiuan, San Jose, CA, and Ding, Yunfei, Fremont, CA, for a “data storage device reverse biasing head element to counter electro-migration.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device is disclosed comprising a first head actuated over a first disk surface, the first head comprising a plurality of elements including a first element. During a first write operation of the first head, a first bias signal having a first polarity is applied to the first element, and a write interval of the first write operation is measured. During a non-write mode of the first head, a second bias signal having a second polarity opposite the first polarity is applied to the first element during a reverse bias interval that is based on the write interval of the first write operation.”

The patent application was filed on March 21, 2019 (16/360,902).

Spin transfer torque (STT) device with template layer for heusler alloy magnetic layers
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,566,015) developed by Freitag, James Mac, Sunnyvale, CA, Gao, Zheng, Hashimoto, Masahiko, Oh, Sangmun, and Zeng, Hua Al, San Jose, CA, for a “spin transfer torque (STT) device with template layer for heusler alloy magnetic layers.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A spin transfer torque (STT) device has a free ferromagnetic layer that includes a Heusler alloy layer and a template layer beneath and in contact with the Heusler alloy layer. The template layer may be a ferromagnetic alloy comprising one or more of Co, Ni and Fe and the element X, where X is selected from one or, more of Ta, B, Hf, Zr, W, Nb and Mo. A CoFe nanolayer may be formed below and in contact with the template layer. The STT device may be a spin-torque oscillator (STO) like a STO incorporated into the write head of a magnetic recording disk drive. The STT device may also be a STT in-plane or perpendicular magnetic tunnel junction (MTJ) cell for magnetic random access memory (MRAM). The template layer reduces the critical current density of the STT device.”

The patent application was filed on May 10, 2018 (15/976,606).

Data storage device detecting resistance delta of spin torque oscillator
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (10,566,014) developed by Poss, Joey M., Rochester, MN, for a “data storage device detecting resistance delta of a spin torque oscillator.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device is disclosed comprising a head actuated over a disk, wherein the head comprises a spin torque oscillator (STO) element. The data storage device further comprises a differential amplifier comprising a first input coupled to a first end of the STO element and a second input coupled to a second end of the STO element. A bias current is applied to the STO element, and the bias current is adjusted. A resistance delta of the STO element is detected based on an output of the differential amplifier, wherein the resistance delta corresponds to a bias current level when the STO begins to oscillate.”

The patent application was filed on March 7, 2019 (16/295,889).