Micron Assigned Fourteen Patents

Fabricating semiconductor structures and related semiconductor structures
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,593,766) developed by Hopkins, John D., Boise, ID, for “methods of fabricating semiconductor structures and related semiconductor structures.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate materials, and laterally removing a portion of each of the tier control gate materials to form control gate recesses. A charge blocking material comprising a charge trapping portion is formed on exposed surfaces of the tier dielectric materials and tier control gate materials in the opening. The control gate recesses are filled with a charge storage material. The method further comprises removing the charge trapping portion of the charge blocking material disposed horizontally between the charge storage material and an adjacent tier dielectric material to produce air gaps between the charge storage material and the adjacent tier dielectric material. The air gaps may be substantially filled with dielectric material or conductive material. Also disclosed are semiconductor structures obtained from such methods.”

The patent application was filed on August 1, 2018 (16/052,159).

Three-dimensional memory array
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,593,730) developed by Conti, Anna Maria, Milan, Italy, Redaelli, Andrea, Casatenovo, Italy, and Pirovano, Agostino, Milan, Italy, for “methods of fabricating semiconductor structures and related semiconductor structures.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An example three-dimensional, (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.”

The patent application was filed on October 10, 2018 (16/156,194).

Arrays of elevationally-extending strings of memory cells
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,586,807) developed by Xie, Zhiqiang, Meridian, ID, Carlson, Chris M., Nampa, ID, Dorhout, Justin B., Boise, ID, Khandekar, Anish A., Boise, ID, Light, Greg, Meridian, ID, Meyer, Ryan, Parekh, Kunal R., Boise, ID, Pavlopoulos, Dimitrios, Glendale, CA, and Shrotri, Kunal, Boise, ID, for “arrays of elevationally-extending strings of memory cells having a stack comprising vertically-alternating insulative tiers and wordline tiers and horizontally-elongated trenches in the stacks.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative tiers and wordline tiers. The wordline tiers have terminal ends corresponding to control-gate regions of individual memory cells. The control-gate regions individually comprise part of a wordline in individual of the wordline tiers. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions. Charge-storage material of the individual memory cells extends elevationally along individual of the charge-blocking regions. Channel material extends elevationally along the vertical stack. Insulative charge-passage material is laterally between the channel material and the charge-storage material. Elevationally-extending walls laterally separate immediately-laterally-adjacent of the wordlines. The walls comprise laterally-outer insulative material and silicon-containing material spanning laterally between the laterally-outer insulative material. The silicon-containing material comprises at least 30 atomic percent of at least one of elemental-form silicon or a silicon-containing alloy. Other aspects, including method, are also disclosed.”

The patent application was filed on June 11, 2019 (16/437,781).

Charge storage
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,586,802) developed by Tang, Sanh D., Boise, ID, and Zahurak, John K., Eagle, ID, for “charge storage apparatus and methods.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.”

The patent application was filed on August 30, 2017 (15/691,442).

Read voltage calibration based on host IO operations
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,586,602) developed by Malshe, Ashutosh, Muchherla, Kishore Kumar, Singidi, Harish Reddy, Fremont, CA, Feeley, Peter Sean, Ratnam, Sampath, Boise, ID, Tanpairoj, Kulachet, and Luo, Ting, Santa Clara, CA, for a “read voltage calibration based on host IO operations.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.”

The patent application was filed on June 10, 2019 (16/436,567).

Forming array of elevationally-extending strings of memory cells individually comprising programmable charge-storage transistor
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,580,782) developed by Ng, Wei Yeeng, Laboriante, Ian, Greeley, Joseph Neil, John, Tom J., Boise, ID, and Hui, Ho Yee, Meridian, ID, for “methods of forming an array of elevationally-extending strings of memory cells individually comprising a programmable charge-storage transistor.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method of forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising alternating insulative tiers and wordline tiers. A select gate tier is above an upper of the insulative tiers. Channel openings extend through the alternating tiers and the select gate tier. Charge-storage material is formed within the channel openings elevationally along the alternating tiers and the select gate tier. Sacrificial material is formed within the channel openings laterally over the charge-storage material that is laterally over the select gate tier and that is laterally over the alternating tiers. Elevationally-outer portions of each of the charge-storage material and the sacrificial material that are within the channel openings are etched. After such etching, the sacrificial material is removed from the channel openings. After such removing, insulative charge-passage material then channel material are formed within the channel openings laterally over the charge-storage material that is laterally over the wordline tiers. The wordline tiers are formed to comprise control-gate material having terminal ends corresponding to control-gate regions of individual memory cells and to have a charge-blocking region of the individual memory cells laterally between the charge-storage material and individual of the control-gate regions.”

The patent application was filed on February 23, 2018 (15/903,254).

Memory arrays
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,580,776) developed by Juengling, Werner, Meridian, ID, for “memory arrays.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Some embodiments include a memory array having memory cells arranged in rows and columns. The rows extend along a first direction and the columns extend along a second direction, with an angle between the first and second directions being less than 90.degree.. Wordline trunk regions extend across the array and along a third direction substantially orthogonal to the second direction of the columns. Wordline branch regions extend from the wordline trunk regions and along the first direction. Semiconductor-material fins are along the rows. Each semiconductor-material fin has a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. Each channel region is overlapped by a wordline branch. Digit lines extend along the columns and are electrically coupled with the second source/drain regions. Charge-storage devices are electrically coupled with the first source/drain regions.”

The patent application was filed on March 28, 2019 (16/368,361).

Memory read
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,580,502) developed by Tanzawa, Toru, Adachi, Japan, for “memory read apparatus and methods.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. Additional apparatus and methods are described.”

The patent application was filed on January 11, 2019 (16/246,009).

Enhanced flush transfer efficiency via flush prediction
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,573,391) developed by Palmer, David Aaron, Boise, ID, for an “enhanced flush transfer efficiency via flush prediction.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Devices and techniques for enhanced flush transfer efficiency via flush prediction in a storage device are described herein. User data from a user data write can be stored in a buffer. The size of the user data stored in the buffer can be smaller than a write width for a storage device subject to the write. This size difference results in buffer free space. A flush trigger can be predicted. Additional data can be marshalled in response to the prediction of the flush trigger. The size of the additional data is less than or equal to the buffer free space. The additional data can be stored in the buffer free space. The contents of the buffer can be written to the storage device in response to the flush trigger.”

The patent application was filed on December 3, 2018 (16/208,165).

Memory device with signal control mechanism
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,559,343) developed by Yamashita, Akira, and Asaki, Kenji, Sagamihara, Japan, for a “memory device with a signal control mechanism.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory device includes an internal storage unit configured to store mode data specifying an operating speed of the memory device, a control decoder coupled to the internal storage unit, the control decoder configured to generate a delay control signal based on the mode data, and an input buffer coupled to the control decoder, the input buffer configured to adjust a delay of an input signal based on the delay control signal.”

The patent application was filed on July 10, 2019 (16/508,162).

Solid state drive controller
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,545,695) developed by Post, Samuel D., San Jose, CA, and Anderson, Eric, Sacramento, CA, for a “solid state drive controller.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory device may comprise circuitry to adjust between latency and throughput in transferring information through a memory port, wherein the circuitry may be capable of configuring individual partitions or individual sectors as high-throughput storage or low-latency storage.”

The patent application was filed on February 16, 2017 (15/434,503).

SLC cache management
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,545,685) developed by Tanpairoj, Kulachet, Santa Clara, CA, Jean, Sebastien Andre, Meridian, ID, Muchherla, Kishore Kumar, Malshe, Ashutosh, Fremont, CA, and Huang, Jianmin, San Carlos, CA, for a “SLC cache management.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.”

The patent application was filed on August 30, 2017 (15/690,869).

Forming NAND cell units
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,529,834) developed by Hu, Yongjun Jeff, Boise, ID, for “methods of forming NAND cell units and NAND cell units.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.”

The patent application was filed on April 30, 2018 (15/967,457).

Namespace management in non-volatile memory devices
Micron Technology, Inc., Boise, ID, has been assigned a patent (10,503,404) developed by Frolikov, Alex, San Jose, CA, for a “namespace management in non-volatile memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A computer storage device having: a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: divide a contiguous logical address capacity into blocks according to a predetermined block size, and maintain a data structure to identify: free blocks are available for allocation to new namespaces, and blocks that have been allocated to namespaces in use. Based on the content of the data structure, non-contiguous blocks can be allocated to a namespace, and logical addresses in the namespace can be translated to physical addresses for addressing the non-volatile storage media of the storage device.”

The patent application was filed on October 23, 2017 (15/790,979).