Sunrise Memory Assigned Two Patents

Three-dimensional NOR strings with segmented shared source regions
Sunrise Memory Corporation, Fremont, CA, has been assigned a patent (10,608,008) developed by Harari, Eli, Saratoga, CA, and Cernea, Raul Adrian, Santa Clara, CA, for “3-dimensional NOR strings with segmented shared source regions.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared bit line and each source line segment are formed in the first and second semiconductor sublayers, respectively.”

The patent application was filed on June 12, 2018 (16/006,612).

3D vertical NOR flash thin-film transistor strings
Sunrise Memory Corp., Fremont, CA, has been assigned a patent (10,593,698) developed by Harari, Eli, Saratoga, CA, for a “three-dimensional vertical NOR flash thin-film transistor strings.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.”

The patent application was filed on October 4, 2019 (16/593,642).