R&D: Latency Constraint-Aware Scheduler for NVMe SSD

IEEE Xplore has published, in 2019 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) proceedings, an article written by Cheng-Yu Li, Jih-Hsiang Cheng, and Ya-Shu Chen, National Taiwan University of Science and Technology, Department of Electrical Engineering, Taipei, Taiwan.

Abstract: “Non-Volatile Memory Express (NVMe) solid-state drives (SSDs) provide high data transfer rates by the benefited from the multi-queue interface and high-speed bus. With a better tradeoff between power and performance, the NVMe SSD is becoming ideal storage for embedded systems. Although multiple dispatch queues supporting increased the data rates, the interference between applications affects the response time of applications which have latency constraints in the embedded systems. In this study, we propose a latency constraint-aware scheduler to manage the response time of applications while maintaining the throughput of the NVMe SSD.“