Intel Assigned Eight Patents

Erase block granularity eviction in host based caching
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,402,338) developed by Jakowski, Andrzej, and Karkra, Kapil Kumar, Chandler, AZ, for “method and apparatus for erase block granularity eviction in host based caching.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”In one embodiment, a processor comprises a processing core, and a cache controller to send a plurality of write requests to a cache storage device to store cache lines of a stream block, the plurality of write requests each including a stream identifier of the stream block, wherein a capacity of the stream block is equal to a capacity of an erase block of the cache storage device and wherein the erase block is dedicated to storing cache lines of the stream block, determine to evict the stream block from the cache storage device based upon a determination that space is not available in the cache storage device to cache data received from a first storage device, and send a deallocation request to the cache storage device to deallocate all cache lines of the stream block to enable the cache storage device to erase the erase block.”

The patent application was filed on April 1, 2017 (15/477,037).

Persistently caching storage data in page cache
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,402,335) developed by Kumar, Sanjay K., Hillsboro, OR, Subbareddy, Dheeraj R., Portland, OR, and Jackson, Jeffrey R., Newberg, OR, for “method and apparatus for persistently caching storage data in a page cache.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”In one embodiment, an apparatus comprises a memory to store executable instructions of an operating system and a processor to identify a request for data from an application, determine whether a persistent page cache stores a copy of the data, wherein the persistent page cache is directly addressable by the processor and is to cache data of a storage device that is not directly addressable by the processor, and access the data from the persistent page cache.”

The patent application was filed on March 31, 2017 (15/476,126).

Drive-based storage scrubbing
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,394,634) developed by Chagam Reddy, Anjaneya R., Chandler, AZ, for a “drive-based storage scrubbing.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatuses, systems and methods are disclosed herein that generally relate to distributed storage, such as for big data, distributed databases, large datasets, artificial intelligence, genomics, or any other data processing environment using that host large data sets or utilize big data hosts using local storage or storage remotely located over a network. More particularly since large scale data requires many storage devices, scrubbing storage for reliability and accuracy requires communication bandwidth and processor resources. Discussed are various ways to use known storage structure, such as LBA, to offload scrubbing overhead to storage by having storage engage in autonomous self-validation. Storage may scrub itself and identify stored data failing data integrity validation, or identify unreadable storage locations, and report errors to a distributed storage system that may reverse-lookup the affected storage location to identify, for example, a data block at that location needing correction.”

The patent application was filed on June 30, 2017 (15/640,229).

Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,379,855) developed by Hasenplaugh, William C., Boston, MA, Newburn, Chris J., South Beloit, IL, Steely, Jr., Simon C., Hudson, NH, and Sury, Samantika S., Westford, MA, for “processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate a packed data register of the plurality of packed data registers that is to store a source packed memory address information. The source packed memory address information is to include a plurality of memory address information data elements. An execution unit is coupled with the decode unit and the plurality of packed data registers, the execution unit, in response to the instruction, is to load a plurality of data elements from a plurality of memory addresses that are each to correspond to a different one of the plurality of memory address information data elements, and store the plurality of loaded data elements in a destination storage location. The destination storage location does not include a register of the plurality of packed data registers.”

The patent application was filed on September 30, 2016 (15/283,259).

Secure memory
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,372,625) developed by Branco, Rodrigo R., Hillsboro, OR, and Gueron, Shay, Haifa, Israel, for a “secure memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Various examples are directed to systems and methods for securing a data storage device. A storage controller may receive a read request directed to the data storage device. The read request may comprise address data indicating a first address of a first storage location at the data storage device. The storage controller may request from the data storage device a first encrypted data unit stored at the first memory element and a first encrypted set of parity bits, such as Error Correction Code, (ECC) bits, associated with the first storage location. An encryption system may decrypt the first encrypted set of parity bits to generate a first set of parity bits based at least in part on an a first location parity key for the first address.”

The patent application was filed on December 27, 2016 (15/391,229).

Techniques for command validation for access to storage device
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,360,176) developed by Tamir, Eliezer, Bait Shemesh, Israel, Makhervaks, Vadim, Austin, TX, Friedman, Ben-Zion, Jerusalem, Israel, Cayton, Phil, Portland, OR, and Willke, Theodore L., Tacoma, WA, for “techniques for command validation for access to a storage device by a remote client.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Examples are disclosed for command validation for access to a storage device maintained at a server. In some examples, a network input/output device coupled to the server may receive the command from a client remote to the server. For these examples, elements or modules of the network input/output device may be capable of validating the command and reporting the status of the received command to the client. Other examples are described and claimed.”

The patent application was filed on January 16, 2013 (13/997,996).

Authenticating system to enable access to diagnostic interface in storage device
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,355,858) developed by Collier, Brandon, Beaverton, OR, Bowen, Thomas R., Albuquerque, NM, Pearson, Adrian R., Hillsboro, OR, and Cox, Jason R., Longmont, CO, for “authenticating a system to enable access to a diagnostic interface in a storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Provided are an apparatus, system, and method authenticating a system to access diagnostic interface in a storage device. The storage device includes a computer readable storage medium implemented to store data and a controller. The controller receives a request from the computer system to initiate a cryptographic nonce to access diagnostic interface in the storage device. The controller generates a nonce and returns to the computer system. Upon receiving an unlock request from the computer system to access the diagnostic interface including a signed nonce comprising at least the nonce encrypted with a private key by the authorized unlock system, the controller uses a public key that is a cryptographic pair with the private key to decrypt the signed nonce to determine whether to grant the computer system access to the diagnostic interface in the storage device.”

The patent application was filed on March 30, 2016 (15/086,040).

Techniques for moving data between network input/output device and storage device
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,353,631) developed by Vasudevan, Anil, Portland, OR, Minturn, Dave B., Hillsboro, OR, and Patil, Kiran, Portland, OR, for “techniques for moving data between a network input/output device and a storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Examples are disclosed for moving data between a network input/output, (I/O) device and a storage subsystem and/or storage device. In some examples, a network I/O device coupled to a host device may receive a data frame including a request to access a storage subsystem or storage device. The storage subsystem and/or storage device may be located with the network I/O device or separately coupled to the host device through a storage controller. One or more buffers maintained in a cache for processor circuitry may be used to exchange control information or stage data associated with the data frame to avoid or eliminate use of system memory to move data to or from the storage subsystem and/or storage device. Other examples are described and claimed.”

The patent application was filed on July 23, 2013 (13/948,715).