R&D: High Performance of MLC Phase Change Memory Device With Endurance Reliability

IOP Publishing Ltd. has published an article written by YuanGuang Liu, Shanghai Institute of Microsystem and Information Technology, Shanghai, 200050, China, YiFeng Chen, Shanghai Institute of Microsystem and Information Technology, Shanghai, Shanghai, China, Daolin Cai, YaoYao Lu, Lei Wu, Shanghai Institute of Microsystem and Information Technology, Shanghai, China, Shuai Yan, Shanghai Institute of Microsystem and Information Technology, Shanghai, Shanghai, China, Yang Li, Junjie Lu, Shanghai Institute of Microsystem and Information Technology, Shanghai, 200050, China, Li Yu, Chinese Academy of Sciences, Shanghai, China, and Zhitang Song, Shanghai Institute of Microsystem and Information Technology, Shanghai, China.

Abstract: “Multilevel-cell (MLC) phase change memory (PCM) usually evaluated in the program method, delay or write energy while the endurance characteristic has not been focused on. In this paper, we exploit a staircase-up program and verify (P&V) method in the current-driven 4Mb PCM chip to achieve MLC storage. The direct results of the change in the R-I characteristic and resistance distribution during the cycles are displayed. According to the measurement, the PCM device shows four separable resistance levels after 1e6 operation cycles with a decreasing resistance of full-crystalline state. And the resistance drift and read disturb which affect the cell reliability also are briefly tested. The MLC device shows a good performance where four resistance levels can be separated well after 1000 second and the read endurance under 0.3V is retained up to 1e9 cycles.“