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Supermicro Assigned Two Patents

Server having removable storage structure, low capacity latency storage enclosure with logic device

Server having removable storage structure
Super Micro Computer Inc., San Jose, CA, has been assigned a patent (10,317,949) developed by Lin, Te-Chang, Shen, William, and Liang, Pan-pan, San Jose, CA, for a “
server having removable storage structure.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A server having a removable storage structure is provided. The server includes a housing, a storage case and a handle structure. The housing includes a bottom plate, a first plate and a second plate. The first plate includes a guiding slot. The storage case is arranged between the first plate and the second plate. The storage case includes a support plate, a partition plate and a heat dissipating plate. The partition plate is in contact with the first plate and includes a sliding slot. The handle structure includes a first arm, a second arm, a handle, and a slide pin. The first arm is pivotally connected to the partition plate and includes a through hole. The second arm is pivotally connected to the second plate. The slide pin is inserted in the sliding slot and the guiding slot via the through hole.

The patent application was filed on April 17, 2018 (15/955,514).

Low capacity latency storage enclosure with logic device
Super Micro Computer Inc., San Jose, CA, has been assigned a patent (10,296,228) developed by Tseng, Kelvin, San Jose, CA, Shih, Trina, San Francisco, CA, Liang, Lawrence H., and Chen, Richard, San Jose, CA, for a “
low capacity latency storage enclosure with logic device.

The abstract of the patent published by the U.S. Patent and Trademark Office states: A storage enclosure includes a plurality of hard drive sub-boards, each configured to include a plurality of hard drives. Each hard drive sub-board is coupled to one or more expanders, via and interface unit, with a set of dual-pass shielded cables. The expander includes a plurality of chipsets coupled to a complex logic device. Each chipset may communicate with a different subset of hard drives with potentially different timing characteristics. The dual-pass shielded cables may be arranged to mitigate these differences. In addition, pin assignments associated with the cables may be set in order to further mitigate the timing differences.

The patent application was filed on April 18, 2016 (15/132,135).

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