PCI-SIG Achieves 32GT/s With PCIe 5.0 Spec

PCI-SIG announced PCIe 5.0 specification, reaching 32GT/s transfer rates, while maintaining low power and backwards compatibility with previous technology generations.

“New data-intensive applications are driving demand for unprecedented levels of performance,” said Al Yanes, chairman and president, PCI-SIG. “Completing the PCIe 5.0 specification in 18 months is a major achievement, and it is due to the commitment of our members who worked diligently to evolve PCIe technology to meet the performance needs of the industry. The PCIe architecture will continue to stand as the defacto standard for high performance I/O for the foreseeable future.“

“For 27 years, the PCI-SIG has continually delivered new versions of I/O standards that enable designers to accommodate the never-ending increases in bandwidth required for next generation systems, while preserving investments in prior generation interfaces and software,” noted Nathan Brookwood, research fellow, Insight 64. “Over that period, peak bandwidth has increased from 133MB/s (for the first 32-bit parallel version) to 32Gb/s (for the V4.0 by16 serial version), a 240X improvement. Wow! The new PCIe 5.0 standard doubles that again to 64Gb/s. Wow2. We have come to take this increased performance for granted, but in reality, it takes a coordinated effort across many members of the PCI-SIG to execute these transitions so seamlessly.“

PCIe 5.0 spec highlights:

• Delivers 32GT/s raw bit rate and up to 128GB/s via x16 configuration

• Leverages and adds to the PCIe 4.0 specification and its support for higher speeds via extended tags and credits

• Implements electrical changes to improve signal integrity and mechanical performance of connectors

• Includes backwards compatible CEM connector targeted for add-in cards

• Maintains backwards compatibility with PCIe 4.0, 3.x, 2.x and 1.x

The new specification increases performance in the high-performance markets including AI, ML, gaming, visual computing, storage and networking.

“AMD congratulates PCI-SIG on the release of the PCIe 5.0 specification to the industry and the future 2x increase in performance it is expected to deliver. We expect to bring our first PCIe 4.0 specification CPUs to market this year and look forward to meeting the future bandwidth demands of end-users with PCIe 5.0 technology,” said Gerry Talbot, corporate fellow, technology and engineering group, AMD.

“Completed in under two years, PCI e 5.0 technology is poised to quickly become the connectivity backbone in the next generation of servers. Astera Labs, a provider of innovative connectivity solutions, supports the new technology and emerging heterogeneous compute topologies with purpose-built signal conditioning products that enable robust PCIe 4.0 and PCIe 5.0 interconnects,” said Sanjay Gajendra, chief business officer, Astera Labs.

“PCI-SIG’s announcement of the PCIe 5.0 specification is a significant step that addresses the increasingly demanding requirements for compute and networking applications. The doubling of bandwidth to 32GT/s can significantly reduce the I/O bottleneck and bolster overall application performance. As an ongoing contributor to the development of the PCIe specification, Cadence supports this latest release with complete, high-quality PHY and controller IP, and verification IP including the TripleCheck verification technology. This comprehensive Cadence offering allows customers to get to market faster with a robust, high-performance solution while reducing development costs and risk,” said Amjad Qureshi, corporate VP, R&D, IP group, Cadence Design Systems.

“Diodes Incorporated is the leading supplier of PCIeproducts including signal conditioning, timing, signal and packet switches for over a decade. Huge growth in cloud computing is demanding higher performance storage and networking infrastructure, hence driving the need for faster peripheral connectivity. We are pleased that the PCI-SIG is releasing PCIe 5.0 specification at 32GT/s to drive faster connectivity,” said Kay Annamalai, senior director, marketing, Diodes Inc.

“As a world leader in timing products, Epson is proud of its involvement with PCI-SIG in the development of the PCIe 5.0 specification. The evolution of PCIe 5.0 technology to 32GT/s, while maintaining backward compatibility, enables customers to drive innovation in 5G, cloud and enterprise datacenter, AI, and other data-driven applications. With low noise products that ease jitter budgets and simplify the design challenge, Epson stands ready to help as our customers determine their timing needs in support of this new standard.” Said Daisuke Yamaguchi, director, marketing and sales, microdevices, Epson America, Inc.

“Genesis supports the PCI e 5.0 specification release by already providing products that double the bandwidth to 32GT/s and focusing on the next evolution of products in the greater ECO system of solutions of PCIe,” said Mick Felton, director, engineering, Genesis Connected Solutions.

“Intel believes that open standards foster platform innovation, create healthy ecosystems, and accelerate market growth. As a founding promoter of PCI Express architecture, we fully support the newly-released PCIe 5.0 specification, and look forward to continuing the PCI Express specification tradition of high-performance, multi-platform, open interconnect,” said Dr. Debendra Das Sharma, Intel fellow, and director, I/O technology and standards, member, PCI-SIG board of directors, Intel Corporation.

“With the jump to 32Gb/s signaling, the PCI e 5.0 specification is bringing new levels of performance for demanding applications in the HPC, cloud computing, AI, and networking and storage spaces. PLDA brings 23 years of expertise in IP design and an extensive catalog of products and services dedicated to PCIe technology to shorten and secure our customers’ SoC, ASIC and FPGA development cycles. PLDA interface IP for the PCIe 5.0 specification are available today and are already being integrated into SoCs due for tape-out in early 2020,” said Stephane Hauradou, CTO, PLDA.
 
“The exponential growth of data and the ever-increasing demands for higher data center performance, require the fastest data speeds between the compute, the interconnect and the storage infrastructures. The combination of Mellanox high-speed IB and Ethernet solutions, and PCIe 5.0 technology, will empower the next generation of HPC, AI, cloud, database, storage and other applications,” said Gilad Shainer, VP, marketing, Mellanox Technologies, Ltd.

“PCI Express 5.0 technology will advance graphics and high-performance computing by doubling its bandwidth to approaching 64GB/s while maintaining socket compatibility with prior versions of the PCIe specification. We are proud to be part of the PCI-SIG team and look forward to the innovation that will be sparked by this next evolution,” said Michael Diamond, senior director, strategic partnerships, and member, PCI-SIG, board of directors, NVIDIA Corp.

“One of the outstanding features of the PCIe 5.0 specification that sets it apart from other communication standards is the inclusion of the Refclk performance in the specification. By fine tuning various system parameters to minimize the amount of reference clock noise that contributes to data transmission eye closure, PCI-SIG has been able to retain lower cost reference clock technology than competing standards at similar data rates. In addition, because PCI-SIG specifies the reference clock performance as part of the standard, companies like Silicon Labs which supply PCIe technology reference clocks for a variety of applications, can further reduce cost by consolidating volume across multiple customers even though they use PCIe transceivers from different vendors.” said Greg Richmond, director, engineering, Silicon Labs, Inc., and contributing member, PCI-SIG Electrical Working Group.

“As an active member of the PCI-SIG for more than a decade, Synopsys has been heavily involved with helping to define the PCI e 5.0 specification. By providing a complete DesignWare Controller, PHY, and Verification IP solution for PCIe 5.0 to the market early, we have already enabled many customers to successfully tape out their advanced 32GT/s SoCs, with many more expected this year,” said John Koeter, VP, marketing IP, Synopsys, Inc.

“Tektronix is excited about the role of PCI e 5.0 technology in enabling the next generation of datacenters. The doubling of bandwidth to 32GT/s is core to solving datacenter performance and latency challenges enabling maximum throughput from the Ethernet links running at 400Gb/s and beyond. As the industry migrates to PCIe 5.0 architecture, prior generations of PCIe architecture must be tested to maintaining backwards compatibility. It is critical that electrical physical layer testing is performed by a single test platform approved by the PCI-SIG for multiple generations. Tektronix is looking forward to partnering with customers to bring PCIe 5.0 solutions to market with a single approved hardware test platform that scales across all generations of PCIe technology,” said Amy Taylor, GM, wired communications and Mil/Gov, Tektronix, Inc.

“Teledyne LeCroy is fully supportive of the PCI e 5.0 spec and is proud to supply tomorrow’s tools today that will expedite product development utilizing the new speed of 32GT/s. Teledyne LeCroy is driving new technologies with its test equipment and customer supportive solutions like our currently available PCIe 5.0 Summit M5x Protocol Analyzer,” said Joe Mendolia, VP, marketing, protocol solutions group, Teledyne LeCroy, Inc.