HGST Assigned Five Patents

Programming multi-level phase change memory
HGST Netherlands B.V., Amsterdam, The Netherlands, has been assigned a patent (10,037,803) developed by Eleftheriou, Evangelos S., Pantazi, Angeliki, Papandreou, Nikolaos,, Pozidis, Haris, and Sebastian, Abu, Rueschlikon, Switzerland, for a “apparatus and method for programming a multi-level phase change memory, (PCM) cell based on an actual resistance value and a reference resistance value.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An apparatus for programming at least one multi-level Phase Change Memory, PCM) cell having a first terminal and a second terminal. A programmable control device controls the PCM cell to have a respective cell state by applying at least one current pulse to the PCM cell, the control device controlling the at least one current pulse by applying a respective first pulse to the first terminal and a respective second pulse applied to the second terminal of the PCM cell. The respective cell state is defined by a respective resistance level. The control device receives a reference resistance value defining a target resistance level for the cell, and further receives an actual resistance value of said PCM cell such that the applying the respective first pulse and said respective second pulse is based on said actual resistance value of the PCM cell and said received reference resistance value.”

The patent application was filed on December 29, 2016 (15/394,207).

Multi-level phase change
HGST Netherlands B.V., Amsterdam, The Netherlands, has been assigned a patent (10,020,053) developed by Lille, Jeffrey, and Franca-Neto, Luiz M., Sunnyvale, CA, for a “multi-level phase change device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.”

The patent application was filed on January 13, 2017 (15/406,221).

Solid state devices having fine pitch structures
HGST, Inc., San Jose, CA, has been assigned a patent (10,008,542) developed by Shepard, Daniel R., North Hampton, NH, for a “solid state devices having fine pitch structures.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded.”

The patent application was filed on June 14, 2016 (15/181,551).

Dynamically sized reverse map to handle variable size data
HGST Netherlands B.V., Amsterdam, The Netherlands, has been assigned a patent (10,001,924) developed by Sharma, Sandeep, Karnataka, India, and Manchanda, Saurabh, Delhi, India, for a “efficient and dynamically sized reverse map to handle variable size data.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a data stream including one or more data blocks, determine a size of the one or more data blocks, determine a number of mappings needed for a physical block based on the size of a data block and a size of the physical block, the number of mappings being variable for different physical blocks depending on the size of the one or more data blocks storing in the physical block, retrieve a dynamically sized reverse map, the dynamically sized reverse map being a dynamic tree structure, determine a starting location in the dynamically sized reverse map for mappings of the one or more data blocks, and create an entry for the physical block in the dynamically sized reverse map.”

The patent application was filed on March 7, 2016 (15/062,456).

Soft information module
HGST Technologies Santa Ana, Inc., Santa Ana, CA, The Netherlands, has been assigned a patent (9,881,670) developed by Weathers, Anthony Dwayne, Barndt, Richard David, San Diego, CA, and Hu, Xinde, San Jose, CA, for a “soft information module.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A soft information module is coupled between one or more flash memory devices and a decoder. The soft information module receives a putative value of one or more memory cells of the one or more flash memory devices based on a read of the one or more memory cells at an initial read level, and one or more respective indicators of whether the putative value was read at one or more respective different read levels offset from the initial read level, and receives a page indicator for the read. The soft information module determines a cell program region for the read based on the putative value, the one or more respective indicators, and the page indicator, identifies a predetermined confidence value for the region, and provides the confidence value to the decoder for association with the putative value, the confidence value being representative of a likelihood that the one or more memory cells was programmed to the putative value.”

The patent application was filed on September 14, 2015 (14/853,941).